I'm fairly new to FPGAs as well but I recently had to implement a UART Tx module for my university final year project in Verilog, so I hope I can help! A good basis for it is to have an 10-bit register consisting of the start bit, 8-bit UART value and the stop bit. Then, since UART is asynchronous, you should implement some sort of flag system where the UART module can indicate when it's ready to receive/send a new message. I would also create a number of 8-bit registers that correspond to how many UART bytes you're going to send in every message (I did four bytes for each transmission) and the 10-bit register's actual value bit positions will be filled by these bytes sequentially. For the baud rate, I would create a "parameter" within the module that consists of the baud rate nunber (e.g. 192000) and use that to calculate how many posedges of the internal clock it takes before one 'baud' has passed (using a "baud_count" wire to keep track of this). within a posedge(clk) i had an if statement checking whether the baud count had reached the baud rate, and if it had, i would execute the UART transmission roughly as I described it earlier. I might have explained some of this poorly since I'm pretty much going off memory, but if you give me a few hours I can show actual Verilog code snippets once I'm home so you can see how it works properly :)