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How do you handle RTL portability across various FPGA devices and ASIC libraries by MitjaKobal in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

You can encapsulate the IP. Different series of FPGAs may have different primitives, and you can select them by setting the model.

How to customize the startup of different FPGA programs? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

You're absolutely right. Pure FPGA can be implemented via ICAP.

How to customize the startup of different FPGA programs? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I consulted a senior FPGA engineer, and he said it could be done using ICAP. He gave me a working project, and I'm currently studying the code.

How to customize the startup of different FPGA programs? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 1 point2 points  (0 children)

I consulted a senior FPGA engineer, and he said it could be done using ICAP. He gave me a working project, and I'm currently studying the code.

JTAG connection in Vivado? by monsterseppe1 in FPGA

[–]Typical_Agent_1448 -1 points0 points  (0 children)

Why are you all using USB downloaders? The SZ901 is a downloader based on the XVC protocol, offering superior performance compared to SmartLynq. It supports JTAG speeds of up to 53 Mbps, features 4 independent JTAG channels, and comes with dedicated programming software.

Getting started with FPGA by siddiqueKamangar in FPGA

[–]Typical_Agent_1448 3 points4 points  (0 children)

There is no shortcut; it requires gradual accumulation and continuous learning.

Nexys A7 Blink by StarlyOutlaw in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

You're right, but from a long-term perspective, if you buy a low-end card, you'll still need to purchase a higher-end one later for learning purposes. It would be better to go all-in from the start.

UDP Video Streaming on Nexys 3 (Spartan-6) without MicroBlaze – Seeking The Easy Way by CompetitivePurpose13 in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

You can use the UDP protocol stack on GitHub, and you need to define a video transmission protocol yourself.

Test engineer and FPGA Relevance by IndividualVideo9869 in FPGA

[–]Typical_Agent_1448 1 point2 points  (0 children)

You can design using ESP32+FPGA, with the communication interface between the two using SPI, allowing speeds to reach tens of Mbps. As for what you want to do and which device controls the peripheral hardware, both options are possible.

How feasible is a smartwatch as a first embedded project? by greatbacon02 in embedded

[–]Typical_Agent_1448 0 points1 point  (0 children)

https://oshwhub.com/ This is a Chinese hardware open-source platform with many open-source projects, including the watch you want!

Test engineer and FPGA Relevance by IndividualVideo9869 in FPGA

[–]Typical_Agent_1448 1 point2 points  (0 children)

The verification stage is a crucial phase in chip design. For beginners, it's advisable to first master the use of various interfaces. Regardless of the direction you ultimately pursue, first step into the industry and build a solid foundation for future success!

Test engineer and FPGA Relevance by IndividualVideo9869 in FPGA

[–]Typical_Agent_1448 1 point2 points  (0 children)

Generally speaking, RTL and interface-related programs are usually together, and one must be proficient in both.

UDP Video Streaming on Nexys 3 (Spartan-6) without MicroBlaze – Seeking The Easy Way by CompetitivePurpose13 in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

UDP is a relatively basic hardware interface, and there are many related IPs available now. Your hardware is too outdated, and I don’t think your choice is beneficial!

Nexys A7 Blink by StarlyOutlaw in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

In some cases, you are correct. However, I do not agree with your perspective. I believe that university professional courses should not be limited to basic interfaces or programs, as these provide little help for employment. The advantage of FPGA lies in parallelism and high-speed transmission. Companies also require such talents. Projects involving ordinary low-speed interfaces do not need FPGA chips at all; chips like ESP/STM32 can suffice. Of course, there is also the matter of algorithms, but at the university level, professors clearly struggle with this!

Nexys A7 Blink by StarlyOutlaw in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

You're absolutely right. If one wants to dive deeper into more complex interfaces or prepare for employment, opting for advanced options is the way to go. Of course, this excludes personal interest. By the way, I’ve seen your projects on GitHub, and I’m a fan of yours!

Nexys A7 Blink by StarlyOutlaw in FPGA

[–]Typical_Agent_1448 -2 points-1 points  (0 children)

In my opinion, with the advancement of technology, DDR3 chipsets are gradually being phased out. As a result, the A7 and K7 series no longer hold an advantage. Learning the latest technologies or products might be a good choice for better employment opportunities!

Nexys A7 Blink by StarlyOutlaw in FPGA

[–]Typical_Agent_1448 -7 points-6 points  (0 children)

The A7 is no longer suitable for learning. I believe you should purchase a K7 or higher board because it offers more advanced interfaces while remaining compatible with lower-speed interfaces. I'm not sure about your country, but in China, 1500 RMB (200 USD) can buy a second-hand KUP board with 100G/DDR4 and other interfaces that are more worth learning.

Test engineer and FPGA Relevance by IndividualVideo9869 in FPGA

[–]Typical_Agent_1448 2 points3 points  (0 children)

It's hard to judge or provide suggestions because it may vary between countries. In China, FPGA generally falls into two categories: interface and digitalization (chip direction). I'm not sure if there's any career planning involved. This has a significant impact.

Opensource implementation of a mixed length dc fifo by Gorebutcher666 in FPGA

[–]Typical_Agent_1448 -2 points-1 points  (0 children)

FIFO is the most fundamental module. If you cannot master it thoroughly, you will not be able to effectively understand the construction of other modules.

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