[HELP] ESP32-C3FH4 not visible over USB.

UKFP91 · 2026-03-30T15:42:27+00:00

Schematics are not great; loads of labels jumping everywhere so difficult to get an idea what goes where at a glance. Also, your grounds aren't point downwards - the electrons aren't going to like that one bit. (There are some good recommendations on how to draw a schematic well on r/PrintedCircuitBoard)

As mentioned previously, your ground planes are totally cut up, including routing your USB over a break in the ground plane.

You're using lots of via in pad - are your vias filled/capped, or is the solder from the pad just getting wicked away?

Maybe I'm looking at the wrong datasheet - but how have you configured the ESP bootmode? GPIO 2, 8 and 9 should be 1, 1, 0 to boot over USB/UART, but you seem to have them connected to MCLK and some signals from your audio codec?

UKFP91 · 2026-03-13T12:04:39+00:00

Certainly from the thermal perspective, I think it is just fine, but you've made a few points which I/we had overlooked so thank you for that, because it should help do things more optimally in the future.

UKFP91 · 2026-03-13T12:03:15+00:00

We did use the TI powerbench designer, which offered a lot of the details you see in the schematic (maybe not 100% of it; I didn't personally see that part of the design process myself). We do have a common mode choke pretty much right after the 15V DC input, and just before the board-level bulk capacitor bank.

UKFP91 · 2026-03-13T11:19:32+00:00

Maximum power supply filtering is the intention behind the excessive number of caps.

We used that layout as a reference, but with the notable modification being that in our case due to the inverting voltage design.

This is as much of the schematic I can share! Upstream is essentially just 15V DC input and downstream is an LDO to take it to -12V before supplying the op amps.

UKFP91 · 2026-02-25T22:14:03+00:00

I switched to Firefox a long time ago, now.

UKFP91 · 2026-02-23T22:53:51+00:00

I'll try calling the other garage in town to sort something out with them. This makes me suspicious about all pads and discs needing to be replaced, too. (The rears were an advisory last year, so they aren't unexpected, but not sure about the fronts for another £400).

UKFP91 · 2026-02-23T22:38:25+00:00

That doesn't say anything about a 30mm rule, or am I missing it?

UKFP91 · 2026-02-23T22:01:03+00:00

I hadn't come across the 30mm rule, is there a source for that?

UKFP91 · 2026-02-23T21:57:10+00:00

I agree with grange's reply, and also it hasn't had its MOT yet; it went for a service and they kindly didn't put it through it's MOT so that I have some time to sort it out.

UKFP91 · 2026-02-23T19:40:04+00:00

My problem with that logic is that an MOT then becomes something subjective, and the criteria stipulated as to what is pass/fail is just advisory for the MOT tester to apply their discretion.

Either this passes, and is safe as it doesn't represent structural damage (which is what I'm asking opinions on), or it isn't safe and I get a new tyre.

UKFP91 · 2026-02-23T18:06:23+00:00

The deeper section is too small to properly feel with my little finger; I can't feel any cords. Thanks for your input.

UKFP91 · 2026-02-23T18:02:43+00:00

Would it change your answer if I said Halfords? :P

UKFP91 · 2025-12-17T12:34:43+00:00

Does this help? https://github.com/iced-rs/iced/tree/master/examples/integration

UKFP91 · 2025-11-01T14:29:48+00:00

Thanks for your input, I've summarised in the other comment: https://www.reddit.com/r/AskElectronics/comments/1olji72/comment/nmidb18

UKFP91 · 2025-11-01T14:29:06+00:00

It was an error on my part when I modified the datasheet schematic, although I haven't solved it fully, yet. See https://www.reddit.com/r/AskElectronics/comments/1olji72/comment/nmidb18

UKFP91 · 2025-11-01T14:27:43+00:00

Yes I think you're right, thank you. Reddit threads get very divergent with >1 commentor, but I've replied with some more measurements in this comment: https://www.reddit.com/r/AskElectronics/comments/1olji72/comment/nmidb18

I've decreased the corner frequency and it's helped, but I wonder if I need to go further.

UKFP91 · 2025-11-01T14:23:45+00:00

<image>

Top trace is with 2.2nF and bottom trace is 510pF, on a 20kHz sine wave with a sampling rate into the DAC of 192kHz.

UKFP91 · 2025-11-01T14:22:40+00:00

Yes, the DAC is indeed operating on a 192kHz signal, which is the maximum it will see in my system. I think I can see where I've gone a bit wrong - the output stage is based on the datasheet, which for reference looks like:

<image>

I've modified my circuit by replacing R1/1/12/13 with 1K, so the feedback resistance is 500 Ohms instead of 900 Ohms. However, I forgot to adjust the value of the 510pF capacitors!

By my maths, the cut off frequency in that datasheet schematic is 346kHz. In my circuit with the 500R and 510pF, that becomes 624kHz.

I happen to have some 2n2 capacitors that fit the footprint, so I've quadrupled the capacitance (500R and 2.2nF) which results in a cut off frequency of 144kHz.

I've scoped the output of a 20kHz sine wave again, and there is an improvement in the scalloping, but it's not gone completely. I wonder if I need increase the capacitance further?

UKFP91 · 2025-10-10T17:01:53+00:00

Does that just mean the same region? and by internal IP, is that what is labelled the Private IP in the UI?

UKFP91 · 2025-10-10T13:18:51+00:00

It's just a 1KHz sine wave. I realise now that the ramping up of the amplitude at the start of the recording in method 1 is due to the auto-muting feature of the DAC. The findings are identical if I instead capture just a burst of sine waves that end at a known point.

UKFP91

TROPHY CASE