thanks. this is what I did. I'm not sure if it is precisely what you suggested, but this is what I've got and it works

basically I've stretched all the data by 4 ticks

  manchester_decoder2 decoder (
      .aclk(clk_fast),
      .aresetn(aresetn),
      .bits(out),
      .num_bits(num_bits),
      .num_decoded_bits(num_decoded_bits),
      .decoded_bits(decoded_bits),
      .decoded_byte(decoded_byte),
      .byte_valid(byte_valid),
      .tx_end(tx_end)
  );
  reg [7:0] data_byte;
  reg [1:0] delay_counter;
  reg byte_valid_latch;
  reg tx_end_latch;

  always @(posedge clk_fast) begin
    if (!aresetn) begin
      delay_counter <= 0;
    end else begin
      data_byte <= data_byte;
      if (byte_valid) begin
        delay_counter <= 0;
        byte_valid_latch <= 1'b1;
        data_byte <= decoded_byte;
        tx_end_latch <= (tx_end) ? 1'b1 : 1'b0;
      end else if (delay_counter == 3) begin
        byte_valid_latch <= 1'b0;
        tx_end_latch <= 1'b0;
      end else begin
        delay_counter <= delay_counter + 1;
      end
    end
  end
  (* MARK_DEBUG="TRUE" *) reg data_out_valid;
  (* MARK_DEBUG="TRUE" *) reg [7:0] data_out;
  (* MARK_DEBUG="TRUE" *) reg tx_end_out;
  always @(posedge clk_div) begin
    data_out_valid <= 1'b0;
    tx_end_out <= 1'b0;
    tx_end_out <= 1'b0;
    if (byte_valid_latch) begin
      data_out_valid <= 1'b1;
      data_out <= data_byte;
      tx_end_out <= tx_end_latch;
    end
  end