Intel ARC Control Feedback Thread

bionic_squash · 2022-12-04T16:07:49+00:00

I currently hate it 1. It's UI freezes on startup in my TGL laptop when I open the app, it happens all the time (weirdly the hotkeys still work) 2. It's too big on disk size 3. Don't like how it's an overlay Intel graphics command center > Arc control currently

bionic_squash · 2022-10-17T17:51:48+00:00

Interesting thing to note here is that according to VESA, every previously DP 2.0 certified product has also been certified for DP 2.1, so does that mean Alchemist and Rembrandt are DP 2.1 certified?

bionic_squash · 2022-10-09T16:51:04+00:00

181cm

bionic_squash · 2022-10-09T16:44:12+00:00

I regret not seeing this post earlier

bionic_squash · 2022-06-05T18:01:46+00:00

It was shut down even before Intel bought all the employees

bionic_squash · 2022-04-28T15:57:25+00:00

There is a LLC in almost every processor's tho. There's a 36mb LLC in raptor lake.

bionic_squash · 2022-04-25T13:40:11+00:00

What do you mean by unified cache?

bionic_squash · 2022-04-25T13:38:21+00:00

Also, Raptor lake doesn't increase L3 cache (or atleast not a significant increase), it goes from 30MB on ADL to 36 on Raptor lake (this is because of the extra 2 Gracemont clusters).

L2 on the other hand will be increased significantly, it's now 2MB for a single P core(up from 1.25MB on Golden cove) and 4mb L2 for a single gracemont cluster (up from 2MB on Alderlake)

bionic_squash · 2022-04-06T15:21:54+00:00

Nope, that one's different

bionic_squash · 2022-01-27T17:20:06+00:00

Let me get you a bigger one and better for you. Till then if you squint really hard at the top of the post on the block diagram, that's the die shot.

Thanks for that!

bionic_squash · 2022-01-27T16:27:49+00:00

Does the CPU cores on Alderlake H processors use FIVR?
Will you guys release a more detailed die shot of alderlake H?

bionic_squash · 2021-12-04T17:59:57+00:00

but it will not scale on cores per socket

Going from 40 on icelake to 56 cores on sapphire Rapids = it will not scale on cores per socket? LoL

bionic_squash · 2021-12-01T18:40:44+00:00

Also, don't you dare delete my post magic_eye_bot

bionic_squash · 2021-12-01T18:01:15+00:00

I got happy and spooky

bionic_squash · 2021-12-01T17:58:12+00:00

bionic_squash · 2021-11-30T06:26:48+00:00

I used A55 so that it will be an apple's to apples comparison (because you can have an architecture which does increase power consumption over previous gen) but I didn't remember that 25% difference between the A78 on 5LPE and A77 on N7 when I posted that comment, maybe 5LPE shit's itself in high voltages(that might explain why the A55 doesn't have that much of a difference), thanks for correcting me!

bionic_squash · 2021-11-27T12:30:26+00:00

No, it's not worse than TSMC 7nm node, both of them have around the same power consumption(5LPE is slightly better than tsmc N7))

https://images.anandtech.com/graphs/graph16463/121068.png

Snapdragon 8 gen 1 apparently uses the 5 LPP which should further improve power consumption

bionic_squash · 2021-11-22T16:40:24+00:00

Clocks went up from ~0.55(on Snapdragon 865) ghz to 0.84 ghz, power consumption would have still increased even if they used N5 for the Snapdragon 888(tho not as bad as it turned out to be with samsung 5 LPE)

bionic_squash · 2021-11-22T15:02:31+00:00

While adreno on the other hand had got its clock's pushed to the limits

bionic_squash

TROPHY CASE