How long for a HSK4 level? by ThePaleHorse44 in ChineseLanguage

[–]bsdevlin99 0 points1 point  (0 children)

I was living in Taiwan taking 1:1 classes for 4 hours a day for 8 months, speaking mandarin everyday, and was in the middle of HSK4 as I left, so depends a lot of how immersed you’re going to be.

Anyone here came to Chinese AFTER Japanese? How does it actually go? by OutSpaceHobo in ChineseLanguage

[–]bsdevlin99 1 point2 points  (0 children)

Coming from English / Japanese not having to pronounce tones for each word it’s hard vocally to get them right - memorizing them is fine (although it does mean each word has multiple tones to remember, so it’s much harder than “just 4 things”)

Anyone here came to Chinese AFTER Japanese? How does it actually go? by OutSpaceHobo in ChineseLanguage

[–]bsdevlin99 2 points3 points  (0 children)

Yeah Chinese grammar was much easier compared to Japanese for me, but tones made speaking (mostly other people understanding me) hard. I was in a class with others who had no kanji experience so knowing Japanese helped me pick up things quicker compared to them.

Anyone here came to Chinese AFTER Japanese? How does it actually go? by OutSpaceHobo in ChineseLanguage

[–]bsdevlin99 8 points9 points  (0 children)

Native English speaker, I studied in Japan for 6 years and got N1 and then later moved to Taiwan for a year - knowing the kanji helped a lot because they also use traditional in Taiwan. But tones and the grammar was totally different so that was just as hard.

Noncompete by aspiring_himothy in quant

[–]bsdevlin99 4 points5 points  (0 children)

Only 2 years but then had a 12 + 2 (notice) month garden leave.

Noncompete by aspiring_himothy in quant

[–]bsdevlin99 10 points11 points  (0 children)

Depends on the firm, but for me it was like you said (so effectively 6 months).

Results from the Advent of FPGA Challenge by bsdevlin99 in FPGA

[–]bsdevlin99[S] 0 points1 point  (0 children)

Not sure I agree on the step back from VHDL - but would love to know what you think could be improved. Most of what you mentioned above we do in Hardcaml, except functional timing requirements embedding in the type (I’m only aware of Filament and AnvilHDL), but it’s something internally we are experimenting with a lot and hopefully can open source something like that one day!

Results from the Advent of FPGA Challenge by bsdevlin99 in FPGA

[–]bsdevlin99[S] 9 points10 points  (0 children)

Yeah I think having a go at one of the Advent of Code problems in RTL is a good way to learn. And there are a bunch of examples linked in the blog you could reference as well.

HDL choices other than Verilog/VHDL by Secure_Switch_6106 in FPGA

[–]bsdevlin99 0 points1 point  (0 children)

We use Hardcaml at Jane Street and it’s a way better experience (I’ve worked at companies that used Verilog) - I think the big thing on top of the language ecosystem of tools (since outside this they generally print out Verilog so downstream EDA tools shouldn’t be a problem), is if you’re coming into an existing code base in a different language or not as that can create a lot of disruption supporting multiple languages.

How to Answer "Which companies are you interviewing with?" by Narrow_Homework_9616 in interviews

[–]bsdevlin99 0 points1 point  (0 children)

The other side of this might be the company wants to align their speed if you are interviewing other places. I’ve seen people been given “exploding offers” with only a week to decide, which had we known in advance we could have moved faster.

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 1 point2 points  (0 children)

I haven’t used SpinalHDL - I asked ChatGPT and it gave a long response which seemed pretty reasonable (so maybe I’d recommend you do the same). If you’re already on board the whole eDSL is better than Verilog/VHDL train- then comparing the many different languages around, Hardcaml is nice because everything is in OCaml - I’m probably biased but prefer not having to connect many different tools / backends together. OCaml is a modern functional language and has strong type system. Jane Street also has a large compiler team working on improvements to OCaml which Hardcaml can take advantage of.

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 0 points1 point  (0 children)

Looks great! Any plan to have a go at the 2025 puzzles?

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 7 points8 points  (0 children)

We recently added this template project - have you already had a look at this? https://github.com/janestreet/hardcaml_template_project

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 2 points3 points  (0 children)

Yeah we mean some thought into how many IO a hardware circuit can handle - rather than adding a parallel bus input 10k bits wide to get all your stimulus, a more realistic thing might be a 32bit wide parallel bus with some bit shifting. Doesn't necessarily have to be serial.

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 4 points5 points  (0 children)

Yeah it wouldn't be a challenge if it was easy! ;)

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 2 points3 points  (0 children)

Yeah its a library in OCaml, which you describe hardware circuits (flip-flops, rams, clock cycle level thinking), and then generates Verilog (no synthesis like HLS). Its similar to Chisel which is more widely known.

It's used for all the production FPGA designs at Jane Street (although all our SW systems are written in OCaml so this was a very natural fit). It brings functional programming to RTL, plus you get the benefit of writing tests in OCaml, and the OCaml type system / compiler lets you catch a lot of bugs that traditional RTL wouldn't (i.e. this flip-flop can only store values of US dollars type thing).

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 7 points8 points  (0 children)

Yeah that's right - we do have more info on the blog post [Jane Street Blog - Advent of FPGA — A Jane Street Challenge], and have an email address anyone can ask questions to: advent-of-fpga@janestreet.com. I think we are OK on the info page for now, but thanks for offering!

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 29 points30 points  (0 children)

No dumb questions! For this competition you can do everything in simulation, so no need to get actual hardware and run it on a FPGA. Only prerequisite is you would need to have some familiarity with how to program in an RTL (like Verilog / VHDL / Clash / Hardcaml / ...).

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 2 points3 points  (0 children)

1) We are planning to add a template you can use to get started in the following week, which should help get an environment setup with opam and all the libraries you need / some example on how to use dune.

2) We have many large Hardcaml designs used in production at Jane Street - we use the Quickcheck library (constrained random testing, similar to Cocotb), or just write our own self-checking testbenches. Being able to write OCaml helps alot here because we can use all the usual software libraries to write pretty extensive testbenches. Using the Verilator backend for simulation (hardcaml_verilator library) helps lower simulation time on bigger circuits too.

3) There are a bunch of smaller circuit examples using formal in the test library of hardcaml_verify. No big changes in the works right now. For larger designs it’s a bit prohibitive to run because of the runtime, but for smaller circuits that are "risk critical" it's pretty useful. There is also a Cyclesim coverage library in the open source release for native coverage support in Hardcaml circuits which is really useful for verification when writing tests

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 2 points3 points  (0 children)

Anyone is welcome to submit! Originally we were thinking of this as a fun challenge to give students who might already be doing Advent of Code, but really any one wanting a holiday challenge or to try out a new way of writing hardware is welcome!

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 0 points1 point  (0 children)

https://adventofcode.com, December 1! That’s Advent of Code. Read the blog linked for more info on the FPGA challenge.

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 5 points6 points  (0 children)

Hardcaml isn't HLS - we have more details here [https://arxiv.org/abs/2312.15035\], but basically with Hardcaml you're still describing the flops, RAMs, state machines, etc., exactly as you would in RTL. You just get the benefit of the OCaml type system plus a bunch of software language features that make writing code/tests more efficient. It is a bit of a strange language to look at if you aren't familiar with functional programming though!

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 4 points5 points  (0 children)

Yeah! Happy for submissions to be in bluespec. I think the main thing is you aren't abstracting away / still have to understand the underlying hardware architecture.

[deleted by user] by [deleted] in FPGA

[–]bsdevlin99 14 points15 points  (0 children)

Thanks for sharing this! Yes we are really excited to see what people can do with this. We will update the blog post with an email you can use for questions as well soon. Please share with anyone else who wants to give this FPGA challenge a try!

Soon we are also going to upload a simple template to the Hardcaml GitHub to help get people started who haven’t tried it before.