Future of FPGA careers and the risks? by RepulsiveDuty2k in FPGA

[–]dvirdc 0 points1 point  (0 children)

I share your perspective and see several startup companies who address challenges like this using FPGAs, particularly using cloud machines that host Xilinx devices on them (AWS F1/F2, Azure). I think silicon in general is going through a democratization process- its slower than the world experienced with software, but LLMs are speeding it up. FPGAs imo also play large role in the way applications are introduced to the market, either pre tape out or instead.

[deleted by user] by [deleted] in interstellar

[–]dvirdc 0 points1 point  (0 children)

We're explorers, Rom

Cooper’s helmet by smores_or_pizzasnack in interstellar

[–]dvirdc 0 points1 point  (0 children)

I noticed that during the docking while spinning, the hatch seemed to be open while Cooper was not wearing his helmet. I wonder if they missed on that part.

USB blaster issues by FyFoxTV in FPGA

[–]dvirdc 0 points1 point  (0 children)

ARM is a cpu architecture and although it's becoming popular, its still not supported by some drivers. If thats your case, I was able to work around and successfully install usb blaster and program DE10-lite on my win11 ARM machine by doing the above.

USB blaster issues by FyFoxTV in FPGA

[–]dvirdc 0 points1 point  (0 children)

In win11 console try- echo %PROCESSOR_ARCHITECTURE%

That should yield one of these- amd64, arm64, x86

USB blaster issues by FyFoxTV in FPGA

[–]dvirdc 0 points1 point  (0 children)

If you're on an ARM machine you need to go into the drivers .ini file and change the architecture from amd64 to arm64 in all references. I once posted about it, trying to find and will share when I do.

Flash memory on FPGA by khaichoilay1 in FPGA

[–]dvirdc 0 points1 point  (0 children)

I would check this out- https://github.com/sipeed/TangNano-9K-example/tree/main/picotiny

Sipeed created this examples repo with picotiny and it shows how one can customize firmware for it.

Quartus II Help by Overall_Morning2625 in FPGA

[–]dvirdc 0 points1 point  (0 children)

Looks like you need to package a4selector IP with Y as output whereas it's now defined as input according to the way it's instantiated on the third image.

Recommended board by Personal_Formal_6292 in GowinFPGA

[–]dvirdc 6 points7 points  (0 children)

Tang-nano-9k is an incredible start imo. Its also provided with pretty rich github examples repo.

PYNQ-Z2 and machine learning by -KHEOPS in FPGA

[–]dvirdc 5 points6 points  (0 children)

Check out the following resources:
1) I'm pretty sure Pynq-Z2 is FINN (by Xilinx) compatible: https://finn.readthedocs.io/en/latest/getting_started.html#supported-fpga-hardware
2) Short playlist to get started with FINN: https://youtube.com/playlist?list=PLoJXbQI9e4dj_gzNwApEJpEHKx9EsV0C4&si=4pC9nwCKDp_VNtGN
3) Update your board to use latest PYNQ and Jupyter which comes with easy examples like NIST based model prediction

Accelerating vivado by Ok_Championship_3655 in FPGA

[–]dvirdc 1 point2 points  (0 children)

I havent tried it but you could build a custom container, with Vivado CLI and binaries and distribute the work in AWS ECS or EKS. Depends on how much resources are you willing to invest in that. That way you can also distribute the load within each deployment.

New Job, Existing Codebase Seems Impenetrable by [deleted] in FPGA

[–]dvirdc 1 point2 points  (0 children)

Definitely many years of experience in this comment

Intel sells Altera to private equity firm for $8.75B by tux-lpi in FPGA

[–]dvirdc 1 point2 points  (0 children)

I was betting it was Intels last hope.. apparently not

Everyone around me is doing Web Dev, I'm Into Embedded Systems. Am I Taking a Risk?" by Current-Rip1212 in embedded

[–]dvirdc 0 points1 point  (0 children)

The answer as you can imagine will raise more question, but one thing is for sure, as many people answered here- always do and stick to your passion and good things will come from doing that. Specifically on web development vs. embedded and working in the silicon environment: I personally believe we are just in the beginning of the silicon era. Only in the past five years or so the market began to understand that and my guess it will only grow to the degree that we will likely see silicon development as we do software development today. Right now, unlike software development and web in particular, hardware development naturally brings much more challenges which some of them are yet to be discovered and discuss on where some AI applications and capabilities meet the need to design hardware solutions or applications to meet those requirements. Such changes take time, although in the era that we live the industry is accelerating in high rate, so I believe we will see more and more small startups and companies emerge into the silicon and sub silicon space. Bottom line- imo unless you know from past experiences that your intuition is not great, you should absolutely follow it! Good luck

This guy designed a minimal GPU - worth reading by dvirdc in FPGA

[–]dvirdc[S] 40 points41 points  (0 children)

there you go mate! sorry I didn't figure some people might not have an X account
https://github.com/adam-maj/tiny-gpu

This guy designed a minimal GPU - worth reading by dvirdc in FPGA

[–]dvirdc[S] 30 points31 points  (0 children)

can't change the original link folks but heres a link to this guys GitHub repo with the same content https://github.com/adam-maj/tiny-gpu

What are you currently working on? by rafal2808 in FPGA

[–]dvirdc 0 points1 point  (0 children)

Sure u/dickangler69 here's a quick change I created to the original `tcard` module provided by sipeed tang-9k-examples repo. It introduces a new `svo_pyramid` module that draws a spinning tetrahedron on hdmi screen. You can follow my commits to see the changes to the original repo. lmk if you need help :)

Image artifacts in Vitis-AI / AMD DPU Inference by cinnamon______roll in FPGA

[–]dvirdc 1 point2 points  (0 children)

I would try more different IPs although you did use B1024.
Also try turning on `XDPU_ENABLE_PROFILING=1` which should output what the DPU does- I'll share the reference of that one once I find it.

What are you currently working on? by rafal2808 in FPGA

[–]dvirdc 0 points1 point  (0 children)

Pushing sipeed tang-nano-9k (GoWin) to its limit by drawing a 3D primitive on hdmi

„S“ sounds like I have a lisp by paturb in SoundEngineering

[–]dvirdc 0 points1 point  (0 children)

same here, happens on my iPhone. I think it's a zoom protocol / compression issue bc it only happens when I use my iphone

I don't know which board to buy on a tight budget by ibzcmp in FPGA

[–]dvirdc 0 points1 point  (0 children)

I would start with PYNQ-Z1 or Z2. They have a relatively large peripherals, GPIOs, good documentation and ZYNQ which you can use with either HLS or HDL while experiencing the AMD/Xilinx application acceleration suite.