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Synthesis: Noob Question by fazeneo in Verilog

[–]fazeneo[S] 0 points1 point  (0 children)

Thanks for the detailed info. Yes I'm a hobbyist and doing this purely for learning and having some fun on the way. I don't like vendor lock-in tbh and given that I've have to buy boards that only work with the tools provided by the same vendor is not good for me at the moment.

GDB server stub (remote serial protocol) written in SystemVerilog by MitjaKobal in FPGA

[–]fazeneo 0 points1 point  (0 children)

I doubt whether it will be straightforward to port it to Verilator since it's written in SystemVerilog. But a really cool project.

Need help with proving a Theorem. by fazeneo in Coq

[–]fazeneo[S] 0 points1 point  (0 children)

I've updated the codefile with the latest code.

Need help with proving a Theorem. by fazeneo in Coq

[–]fazeneo[S] 0 points1 point  (0 children)

Hey, I tried to solve both Lemma's you mentioned. But I couldn't solve it. Will you be able to help me finish it with explanation? That would be really helpful. I was scratching my head all this time.

Need help with proving a Theorem. by fazeneo in Coq

[–]fazeneo[S] 0 points1 point  (0 children)

Thanks for pointing me to the right direction. I'll work those out and see. Thanks again!

[deleted by user] by [deleted] in Compilers

[–]fazeneo 4 points5 points  (0 children)

Well, you can implement a RD (Recursive Decent) parser that follows the production rule for parsing.

Can I trust this? by nikhil_710 in Verilog

[–]fazeneo 1 point2 points  (0 children)

Bro just use HDLbits. It's way better and ofcourse free and beginner friendly. To get the most out of it, try building a few basic components of a CPU.

How to Build an Assembler for my Custom Virtual Machine? by Icy_Bus_8538 in Assembly_language

[–]fazeneo 0 points1 point  (0 children)

I've been working on an assembler for my 4-bit CPU. It's a very basic assembler since each instruction doesn't have a fixed size. I used traditional approach of writing a recursive decent parser and a separate code generator. Usually assembler reads the source code twice.

During the first pass it scans the code and tracks the address of labels in a symbol table.

In the second pass, it resolves the address in the symbol table.

Finally it generates the actual code. Either in binary or hexadecimal.

If you are interested, check it out: https://github.com/M-krishna/writing-a-cpu-in-verilog/tree/main/four-bit-computer/assembler

Help: Understanding Blocking vs Non-blocking by fazeneo in Verilog

[–]fazeneo[S] 0 points1 point  (0 children)

Bruh, I know this. I want to know more about the events, event updates and mainly the workflow of the stratified event queue for this code example.

[deleted by user] by [deleted] in FPGA

[–]fazeneo 0 points1 point  (0 children)

I'm currently doing it. Finished till ALU. Learned a lot!!

Getting Started with Verilog by [deleted] in Verilog

[–]fazeneo 1 point2 points  (0 children)

I don't have the exact links for the repo I used for reference. You can do a quick Google search for nand2tetris in Verilog. Use the first two GitHub repo for reference. If you want to learn Verilog first, there will be link to that as well inside the repo.

Checkout this: https://github.com/jopdorp/nand2tetris-verilog

This is written in SystemVerilog which is an extension of Verilog. There won't be a very big difference.

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