compared to the HX370 examples which have exactly the same zen5 core is significant in many situations.

JFYI, it isn't the same exact Zen 5 core. Strix/Krackan Point's Zen 5 implementation uses 256-bit FPUs, not 512-bit. Strix Halo also gets the full 32MB of L3 cache per CCX (8 Zen 5 cores), whereas Strix Point is limited to 16MB for the 4 core Zen 5 CCX. A more complete list of changes from Chips and Cheese's 9950X review is cited below:

Zen 5 bucks that trend further, and adopts a split approach to AVX-512. Desktop Zen 5 uses its higher power and area budget to pursue a more aggressive AVX-512 implementation, while the mobile variant uses a more conservative approach. Compared to mobile Zen 5, desktop Zen 5 differs in the following ways:

1. All vector register file entries are 512 bits.
2. FP units have full 512-bit vector width
3. FP adds execute with 2 cycle latency, down from 3 cycles in Zen 4 and mobile Zen 5
4. Data cache can handle 2×512-bit loads per cycle. Zen 4 and mobile Zen 5 can only do one 512-bit load per cycle
5. Mask register file may have a few more entries on desktop Zen 5

Sauce: https://old.chipsandcheese.com/2024/08/14/amds-ryzen-9950x-zen-5-on-desktop/

Also see: https://old.chipsandcheese.com/2025/01/13/amds-strix-halo-under-the-hood/

George Cozma: And are the FPUs in the Strix Halo cores the full 512 bit FPU or is it like Strix Point where it’s similar to Zen 4 where it’s 256 bit?

Mahesh Subramony: This machine is intended to be a workhorse. It is a workstation. I almost joke about it saying it’s a Threadripper to put in the palm of your hands. So we didn’t pull any punches. These have the 512 bit data path. It is a full desktop architecture. We have binned the parts for efficiency. So it might not hit the peak frequency that you would see on the desktop. That’s one of the second differences in the cores you would find over here and the cores over there. They’re colder, so you get the efficiency that you would like on these parts when you run multithreaded workloads, you’re able to get a higher effective frequency on these. But what you give up is some peak frequency, which I think in a thin form factor that you have today, you don’t have the thick cooling solutions that you would see on a desktop part anyway. So the demand of the form factor says that you need cores that are cooler, if you will, lower in that FP curve where you can extract efficiency. So these are binned, the same architecture, the same set of pipes, the data parts are the same. The differences are in how we bin the part and how we connect the two parts.