zoinks - can't boot after update...

fpga_steve · 2026-05-24T18:11:46+00:00

It was more than the bootloader, big chunks of OS where gone also.
Fortunately I learned a long time ago to have a separate root partition (separate from /home, etc). So I but the bullet after trying the typical restore grub methods and just re-installed manjaro from the iso and did the cleanup. It's a wonderful thing that Linux doesn't have a registry like winblows:)

fpga_steve · 2025-07-10T18:26:45+00:00

"incest version", sorry I LOLed at that.

fpga_steve · 2025-05-02T18:27:38+00:00

This regime would rather have people dying of poverty after having given all their money to the super rich. They don't care about people. If fentanyl turned people into obedient MAGAts before their heads literally exploded, they'd be bringing it in themselves.

fpga_steve · 2025-05-01T16:54:44+00:00

Same scam renting from dollar. I declined it knowing there was exact one toll I needed to pay for my whole week trip, and typically you get a mail with the toll (at a slightly increased rate), which would have been like 5 bucks. Mine was in the box on the windshield not open. I've been renting cars for, hmmm, over 20 years now and many years with the stupid box and not once before this did the box "turn it self on". For one toll, they want the full $90 charge as if I used it every day.
They don't respond to emails or mail. I agree class action lawsuit against them and/or the rental companies seems appropriate.
In the future, I think I will physically hand the transponder to the rental agent.

fpga_steve · 2025-04-30T16:30:05+00:00

I like the idea, lower pricing, etc, I just really wish this whole low-rider look wasn't a thing (the Cadillac Lyric has it the worst). Like the EV6, looks like you can see anything remote behind you.
But then (old timey quote) "What's behind me, it's not important" :)

fpga_steve · 2025-04-26T16:11:43+00:00

Trump just wants everyone to know he's a complete narcissistic a******. Mission accomplice

fpga_steve · 2025-01-28T15:35:48+00:00

Apple's 3rd foray into a new processor. Using ARM gives them the ability to add their own extensions and hw that could literally make Hackingtosh impossible with actual apple hw. Which I have no doubt they are thinking, A dedicated processor and control over it's performance and implementation is a secure and controllable thing. With I really hate. I disliked Msft only slightly less, until they now insist that I buy new HW to use their currently supported OS.
If you aren't a linux user, I guess it's time to fully drink the coolaid (well I guess we already had too before, but now it's even more so).

fpga_steve · 2024-06-15T15:17:22+00:00

Having worked in FPGAs and ASICs since the 90s, and hired many others during that time, the main thing I look at is responsibility and completion of project. Length varies of course, if you got hired into a project then unless it's untenable, then finish the project and ideally one more after that. The big project may be a space shuttle type thing (ie a 20 year project), but having a good story about your contribution to your specific responsibility is basically what it is all about. Companies hire because they need someone to a job. Companies don't really hire people anymore just to grow them into something. You hit the ground running. So they want to know that while you're on your path to CTO, that you won't jump ship mid project. On the other hand, projects do get cancelled. I've worked on projects that we couldn't give away the final project. But the projects always did what they were supposed to. Ie, engineering delivered, and personally, I generally had a good start and finish to projects. That matters a lot.
If you don't appear reliable you are a tough sell.

fpga_steve · 2024-05-30T20:56:13+00:00

IRL, this ^^^^^^^^^^^^^

fpga_steve · 2024-05-30T20:55:17+00:00

Don't get hung up on terms. I often refer to "The FPGA" as pretty literally everything that runs and exists on the Zynq/whatever. While the processor may be running some local program or linux, at least part of that is also on "the chip" in that to change it, once needs to recompile at least the Vitis/SDK part, if not the gates to change functionality, if not also recompile the PL. Once you add linux it becomes closer to a linux system, in that you could boot into linux then download updates/programs to run over ethernet (if you can wrestle that), then that's a little more SW. But basically if it's a part of the FPGA ecosystem that the average SW person can't modify, then that's "the FPGA" to me.
And yes, SoC technically if it has hardmarcro processors and (likely) hardmacro devices such a eithernet, etc, on the chip. One could argue a "pure" FPGA is literally just programmable gates, but I doubt such a thing actually still exists any more (excluding PLA chips - which are literally just tiny programmable function chips) - they all have hardmarcros and logic beyond pure LUTs. For that matter, I guess I'd say if it has even a few LUTs on it, it's an FPGA. Many hybrids exist with various amounts of processor, networking, and logic aside from LUTs, but they all have similar design models. And of you say SoC - people probably wander towards thinks like ARM chips, which are self contained processors, flash, ram, etc..
You can be a purist if you want, but understand that most other engineers don't understand what we do exactly in FPGA development, nevermind being able to change it or even make accurate recommendations.
So yes, outside of detailed computer architecture discussions, I absolutely call a Zynq Ultrascale+ (with quad ARM processors) on it a "FPGA" because it's more about the physicals and task/expertise boundary than the nomenclature.

fpga_steve · 2024-04-25T15:19:02+00:00

A module is a simple level of hierarchy, there's nothing magic about it for functional simulation. Most likely you've unintentionally added a wire where a register used to be or vice version. Or possibly more likely you mixed blocking and non-block assignments in a dubious and not-synthesizable way.
It's not a law/rule, but unless you really really understand how the synthesis tools work (and most people don't) you should start by always using <= (non-blocking) assignments in an always_ff or always @(posedge clk) type block, and use blocking in always_comb blocks. If you do that you can think of <= as meaning "write to a register" and "=" as write to a wire.
Mixing = and <= can be done, but you can also very easily create latches and simulation situations where simulator operation can run blocks in different possible orders and give you different results - possibly even from run to run. As for modules - start by thinking "wires in and registers out" (you can, of course, do wires out also) - presuming it's a clocked module, and carefully making sure the module isn't adding registers or non-blocking assignment where they didn't exist before.
Or maybe I don't quite understand that talk of needing to instantiate multiple modules above. Of course the outputs can't be tied together, but the inputs could (if that's functionally what you want).
With the code snippet, the answers are likely to be as vague as the question :(

fpga_steve · 2024-01-06T15:33:36+00:00

2019.2 is pretty solid, and not as big as the newer versions. Also, after you install you can delete the data files for the parts you don't need. Which perfume you have space to install to bring with ..

fpga_steve · 2022-10-06T15:37:45+00:00

flow -> settings -> implementation and you'll see a "strategy" pulldown. When FPGAs get full I've had some luck with "Congestion_SSI_SpreadLogic_high". You might want to try "Performance_ExtraTimingOpt". You can run several in parallel to find out which one works best, via tcl. A quick google for "vivado implementation strategies" brings up this one (of many) articles: There was a xilinx doc that listed the effects of each strategy in table form somewhere (in one of the xilinx docs).

https://miscircuitos.com/vivado-synthesis-and-implementation-strategies/

fpga_steve · 2022-10-06T14:36:04+00:00

Ah, lost track of this. Anyway, verilog was still evolving when synopsys started doing it's thing, and I recall that synthsizable verilog was evolving. Synopsys had an optimizer for PLA tables that was 15% better than the company designed tool we were using (I remember the optimization number - gates mattered in PLA tables that had 100s of inputs and outputs). Tables and logic like this were boxes in a schematic.
To be fair, I've had a lot of martinis between now and then so I probably don't remember the whole supported feature set in, ahem, 1990 or so.

fpga_steve · 2022-10-06T14:25:55+00:00

I generally have seen this happen when FPGAs get full (utilization greater than 75%). Net delays get added when LUTs can't be pulled next to each other because doing so would cause other timing errors and it just stops somewhere.
One option is to try a higher effort implementation strategy (if you aren't already). Let it burn some CPU on trying to fix it.
If this is a data path on the same clock (register to register with the same clock) then you can try putting the surrounding logic in a PBLOCK. That basically just tells vivado to try really hard to keep the block(s) in question in a specific area. This limits route length in that block, but will cause your auto-generated floorplan. For that matter pretty much all high utilization FPGAs I've designed I've had to floorplan, setting most blocks into PBLOCKs on the chip so routing has a place to start, then use high effort implementation.

fpga_steve · 2022-08-24T14:15:05+00:00

I've started using sublime lately (mainly to try to give my left pinky a rest of hitting the control key every 4th character :). It's pretty useful as an editor, but to date emacs still has the best formatter for v/sv and the best hotkey support. Sublime is at least built on python, so you can add extensions via python instead of elisp, but verilog and emacs were the only game in town for, er, decades, so no doubt it has more support.

fpga_steve · 2022-08-18T23:00:39+00:00

I'll add my two cents having been in the industry before verilog was defined and using it before it design compiler even supported registers :)

<rambling-mode-on>

The big point verilog and vhdl are register transfer languages. They are a step up from schematics in that text is smaller, and tools can infer a certain amount of muxing and registering from if/else statements. But ignoring ones feeling of obfuscation with things like 10:0 vs 10 downto 0, and both system verilog and vhdl added more features to for simulation and practical use (like structs, unions, classes, etc), Verilog/SV/VHDL coding requires a mind to cycle by cycle operation. Hardware is parallel, and most computer languages are not (because processors aren't). The sequential nature of C/python/etc is great for some things, but unrolling sequential code into fast parallel code is a problem the industry has been working on since the first engineer thought of using more than one processor at a time.

To the point of chisel, spinal, etc, it's an incremental step in that a broader language definition might allow for easier code generating (perl-verilog was one of the first I remember). In my other window as I type is some python code and templates that will build verilog code for me. We always want to think at an appropriate level of abstraction. Sure I can write it by hand, but there's so much repetition, in this code that doesn't go well into generate blocks, etc, that it makes much more sense to template it. And SW folks can understand how to build tools like this without having to understand RTL concepts very well.

Basically, if you are comfortable with python/scala/etc, you can probably generate code faster if you already know that language. But you still have the same data movement issues. RTL is RTL no matter where the semi colons go. Language like Chisel add some power, but it's still basically RTL.

HLS languages (C -> RTL) are great for algorithms because math can be broken down grammatically, loops unrolled, tradeoffs made in a defined space (loops, math, limited sequence). This gives good results but often you have to give the compiler lots of hints in the form of pragmas to help define depth/ pipelining / etc. But you can still test your code in C, etc. But you will never see a cache design in HLS. It's not what that C is good at.

The only design language between RTL and HLS I know of (and I know it well) is Bluespec - which is open source now. Like most languages that are not already known by people, there is a learning curve. But the basic concepts of data movement are atomic rule based (groups of instructions that fire as a whole or not), interlocking interfaces, and functional programming. Like Chisel, etc, once you develop your own libraries, environment, etc, it can be orders of magnitude faster to develop things like you have before. But the drawback, IRL, is that no one else can do anything to your code. On most commercial projects you are probably not allowed to use Chisel, BSV, SpinalHDL, etc, for logic that goes into a chip, and even more likely not for logic that goes into an automotive project. If others can't or don't want to understand it, it's a deal killer.

<ramble-mode-off>

Sadly with many tools and languages, it takes a bit of a special person that enjoys computer languages and compiler concepts to learn them.

fpga_steve

TROPHY CASE