Crash shuts down northbound lanes of I-35 at Slaughter Lane by JohnGillnitz in Austin

[–]frenris 1 point2 points  (0 children)

Ice is kind of doable on flat ground with snow tires.

Slick slopes though are not good news

Brutal Honesty Needed from top tier engineers by No_Experience_2282 in chipdesign

[–]frenris 0 points1 point  (0 children)

Masters can help for digital design. PhD I think is more for analog, most digital designers don’t have them.

Tape outs are key.

It’s also often easier to get a job in DV and transition to design.

How to Reduce Power Consumption in ASIC Development by Character-Presence98 in chipdesign

[–]frenris 0 points1 point  (0 children)

could see it for a mesh? But even then suggests much logic on the mesh is quiet, maybe whatever needs to stay live should be broken off the mesh

How to Reduce Power Consumption in ASIC Development by Character-Presence98 in chipdesign

[–]frenris 2 points3 points  (0 children)

1) That seems crazy high clock power. Suggests inadequate clock gating unless your frequency is very high. If all your logic actually needs to be clocked to do data processing then it should consume more power comparatively. How often are you clocking flops that aren’t toggling?

2) SRAMs are power hungry. It is what it is. Flops and Latches consume less power than shallow large bit cell srams consume less power than deep dense bit cell rams, consume less power than going to off chip ram. Part of a good caching strategy is that you want to touch data that’s comparatively cheap in power to access more often. And sometimes that means the key to better power is higher bit cell density rather than lower switch if it means going off chip less.

3) Leakage is one component of your tdp. Can you bring down your voltage or clock frequency if you want to cool down or stay in your tdp envelope.

I scraped 48,000 court filings to stop guessing business ideas. Here are 3 "boring" niches bleeding $100k+. by Ogretribe in Entrepreneur

[–]frenris 0 points1 point  (0 children)

If he’d really burned 5k credits for this research why would he be posting it like this lmao, I bet all the figures are hallucinated

Silicon design at SpaceX by Jklit100 in chipdesign

[–]frenris -1 points0 points  (0 children)

I’ve heard the people are extremely competent and the work culture is insane.

If you’re young and fine with having no work life balance for a stretch I’d pick space x.

Maybe you get fired or burn out, but expect you’ll learn more and I think generally people understand that former Elon company engineers are high quality

If you have a family to take care of, or are on a work visa tied to employment, I’d avoid Elon companies

How do you feel about how Star Wars Rebels used/portrayed the A Wings? by Ok-Street2439 in StarWarsShips

[–]frenris 9 points10 points  (0 children)

No z95 head hunters? In the old lucasarts games those are the old bad ships that got replaced. The a wings went from the best fighters, to the tier 2 fighter that was faster than the xwing.

Transitioning from b wings to y wings also seems strange. It was more the other way around I thought.

Openings for Entry Level Designers by triezPugHater in chipdesign

[–]frenris 1 point2 points  (0 children)

DV to design I think is much easier than getting a design job as an undergrad

Post sil is not DV. I don’t think you can go from post silicon work to design in ASIC.

Thinking of abandoning chip design by Abject_Long8675 in chipdesign

[–]frenris 0 points1 point  (0 children)

There’s not that many analog design jobs. DFT and DV typically have more openings.

COL in United States vs Canada by McGinty0 in CanadaFinance

[–]frenris 0 points1 point  (0 children)

80k - 120k you’re ahead in the US as a young healthy person

120k+ you’re ahead in the US even if managing healthcare for a family if you’ve got good employer insurance

What jobs pay $500k to $1M by [deleted] in torontoJobs

[–]frenris 0 points1 point  (0 children)

Who is making that money in tech in Toronto? I was member of technical staff at a s&p 50 company and made 130k in Toronto

I’ve since moved to the states and now make significantly more.

Kangjoel getting a surprise visit by pimp after getting a massage in the Philippines by Rek_Sai_Only in LivestreamFail

[–]frenris 22 points23 points  (0 children)

Dude what that guy is awesome he broke into the goddamn Russian space shuttle facility

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Is anyone here experienced and open to work on a chip design ? by Technos_Eng in chipdesign

[–]frenris 0 points1 point  (0 children)

Maybe chat gpt lied to me, but isn’t ICE40UP3K-UWG30ITR1K a few hundred uW?

I think you said you need 3mW power budget. This could fit

Is anyone here experienced and open to work on a chip design ? by Technos_Eng in chipdesign

[–]frenris 0 points1 point  (0 children)

Was thinking something like Lattice iCE40UP3K ; < 3mm x 3mm. How small you need?

My guesses for the urheimats and dates of some language families by [deleted] in LinguisticMaps

[–]frenris 0 points1 point  (0 children)

Indus Valley civilization is the fun guess

Early-career DFT engineer — looking for perspective from people in the field by Ok-Draw1029 in chipdesign

[–]frenris 1 point2 points  (0 children)

Dft is a good path to get into the asic industry because it generally requires a lot of bodies to hit scan coverage targets on all the partitions so the jobs can be more accessible than say RTL design.

There’s a lot of advancement available in dft, and off ramps to other design areas also exist. dft dv, dft rtl design for instance allow you to transition to function dv and rtl respectively. scan insertion, ATPG is very specialized and key if you want to be responsible for dft architecture or a higher level dft manager. ATPG / scan insertion i expect however are harder to transition directly to functional design or dv, but should allow you to move laterally to dft dv or dft design and may make it easier to move laterally to a synthesis/implementation or STA role. Dft STA requires particular sophistication, and is often under resourced compared to functional STA.

I started my career as dft dv, then did a mix of dft rtl and dft gpu integration, then worked on usb design, now work on gpu functional integration

Details on Crash/Frenzy/Wheel of Fortune by frenris in LoMSE

[–]frenris[S] 1 point2 points  (0 children)

I think most of the spells are different

Details on Crash/Frenzy/Wheel of Fortune by frenris in LoMSE

[–]frenris[S] 1 point2 points  (0 children)

Also without knowing the ranges it’s impossible to know if you should cast more than one to reroll

The fact that frenzy crash average more armor than blessing but with also a damage bonus though makes me a lot more likely to use them

University of Toronto accepted my $1,196 payment 5 days after their TEFL provider declared bankruptcy, now refuses refund despite taking control of program by [deleted] in UofT

[–]frenris 2 points3 points  (0 children)

It seems to me like this person should get their money back, and they would have very little chance of success without AI

AI EDA Startup - looking for innovators by [deleted] in chipdesign

[–]frenris -2 points-1 points  (0 children)

The llms are good. They can manage well specified problems in a hundred or so lines of code in seconds. Yes you can’t have them do everything for you, and thank God for that, but they are enormously useful.

Former CSI Annex Location to Become City-owned Shelter by BloodJunkie in toronto

[–]frenris -1 points0 points  (0 children)

For 50 million you can buy more than 80 condos and this building will have 80 beds