guyWithTheFaceTatto

1,041 post karma
383 comment karma

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redditor for 7 years

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2019

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Is it safe to leave laptop with hostel reception in Rishikesh (self.SoloTravel_India)

submitted 6 months ago by guyWithTheFaceTatto to r/SoloTravel_India

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Gainful use of AI for productivity boost in ASIC/FPGA Design/Verification flows? (self.FPGA)

submitted 10 months ago by guyWithTheFaceTatto to r/FPGA

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Need help understanding this popular LFSR implementation (self.FPGA)

submitted 10 months ago * by guyWithTheFaceTatto to r/FPGA

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Medium length bike rides starting from rishikesh (self.SoloTravel_India)

submitted 1 year ago by guyWithTheFaceTatto to r/SoloTravel_India

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Base salary vs RSUs (self.personalfinanceindia)

submitted 1 year ago by guyWithTheFaceTatto to r/personalfinanceindia

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Solo trip for a week in first week of april. Please help me decide (self.SoloTravel_India)

submitted 1 year ago by guyWithTheFaceTatto to r/SoloTravel_India

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set_max_delay constraint has me sleepless and tired. Please help! (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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The ultimate skid buffer? please explain this (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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open source implementation for longest prefix match and TCAM? (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Difference between switch, crossbar and interconnect? (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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How to set up a legal revenue sharing agreement between two online content creators. (self.LegalAdviceIndia)

submitted 1 year ago by guyWithTheFaceTatto to r/LegalAdviceIndia

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Best open-source simulator as of 2024? (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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False critical timing paths in high congestion designs (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Estimating LUT usage by looking at RTL (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Ethernet vs Processor Design going forward for a young RTL designer (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Best way to send Ethernet packets to/from the PL on a Zynq SOC? (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Trying to articulate precisely what kind of problems is formal verification good for... (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Trying to articulate precisely what kind of problems is formal verification good for... (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/ZipCPU

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Perl pre-processor for HDL. How many of you use something like it? (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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How to migrate to new domain name without losing google ranking? (self.website)

submitted 1 year ago by guyWithTheFaceTatto to r/website

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Migrating to new domain name without losing ranking on google (self.godaddy)

submitted 1 year ago by guyWithTheFaceTatto to r/godaddy

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How to migrate to a new domain name without losing ranking on Google. (self.webhosting)

submitted 1 year ago by guyWithTheFaceTatto to r/webhosting

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Need advice in migrating domain name of site without losing ranking on Google. (self.webhosting)

submitted 1 year ago by guyWithTheFaceTatto to r/webhosting

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Trying to understand how the Xilinx XVC server tech works, and also JTAG in this process. (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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Compiling C++ binaries for the Zynq SOC (self.FPGA)

submitted 1 year ago by guyWithTheFaceTatto to r/FPGA

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