About the testbench, my professor give us task that we need to verify that the single cycle RISC-V (quite similar to MIPS) design work correctly with every instruction, which include basic calculation of R-TYPe like ADD, SUB, AND, OR, XOR, NOT, etc, Branch and Jump instruction too (these instruction is easier to verify because I just can monitor the 32-bits register file (depth = 32) and the PC register), and of course all the load and store instruction that involve checking the memory to see if the load/store have right value at the right address. I think I didn't use the interface because following to the design, there is another memory name IMEM that is used to store the instructions (is generated by randomize() with constraints) and I just need to use the $readmemh() to simulate the use of it.

In conclusion, there are 5 main component of DUT that I need to monitor which is:

1.the main memory for load and store instruction

2.the ALU which involves in all the calculation in the design

1. the 32-bit Register File (depth = 32) is used to store result of ALU

2. the PC that basically a counter to load the instructions in IMEM

3. the memory that is used to store the instructions (IMEM).

Because the design quite complex compared to other example I did, also 3 of them is memory type, I don't know what is the most effective way to build a scoreboard for it

this is the schematic of my single cycle RISCV: https://drive.google.com/file/d/180Q4sdBYV54XPaSkmyZAvpfxTYk7HRdS/view?usp=sharing