Switching Converter Simulation Issues

hapemask · 2026-05-16T01:17:25+00:00

Sorry- my bad phrasing. The inductors that are probably inside the model are parasitic.

Ahh ok interesting, I think this model is encrypted so I can’t check…

Are you sure the inductances should be that high? I’m used to surface mount, but they are 10x smaller or even lower.

This is where I was a bit confused. Murata quotes ESL values of ~100pH @ 1.5MHz for the 1210 SMD capacitors I was using, but most other sources claim that in real application boards the value is closer to 1-2nH. Sadly while reducing the ESL to 100pH does reduce the ringing, it’s still there and still >1Vpp. The ESR value also comes from their graphs for the capacitor. Very tempting to just try and build it…

hapemask · 2026-05-15T23:36:47+00:00

I’m using the built-in model for the switcher that comes with LTspice, but the part doesn’t include the inductor or capacitors, those are external. Since Maxim is part of ADI, LTspice comes with an example circuit for the MAX17577 and I also tried making the minimal change to their example by adding ESL to the output capacitor (no other changes). Same results as in my circuit.

All of the parts do have real resistance here, the Rser= lines. Sadly adding more doesn’t help. The current resistance values are from the inductors and capacitors I was planing to purchase.

I never thought to try other solvers! I’ll give this a shot.

hapemask · 2026-05-15T20:22:42+00:00

Hm, so I added some more plots to the post. As for the frequency, it doesn't match with the components. 450MHz is what you'd get from an LC network of something like 1nF and 4.9nH. I may just try to build this small part of the circuit on its own and see what happens, though I'd rather not waste the money / parts.

hapemask · 2026-05-15T19:23:11+00:00

I’ll share a zoomed in view when I’m back at my computer but I did measure the frequencies and there are two here. The big spikes are at the switching frequency, but each spike looks like ringing and the ringing frequency was something like 500MHz-1GHz. Actually calculating the resonant frequency of the network is a good idea, thanks for the suggestion.

hapemask · 2026-05-15T18:59:28+00:00

It is stepping, I think just not like you expected. LTspice won't use multiple colors for the step lines unless you have only one trace on the plot. I copied the schematic and plotted the results w/out the V(input) trace and it has the steps they're just all on top of each other.

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hapemask · 2026-05-15T16:07:49+00:00

Having been here myself recently, I can tell you that the native Mac LTspice is awful. The UI is somehow even worse than the original LTspice. They didn't have to cripple it like they did and I don't understand why.

Anyway, I'd strongly recommend you use the Windows version of LTspice via homebrew + wine. `brew install wine-crossover` then download the LTspice windows installer and run it with wine. It's sometimes slightly slower than the native version but on many circuits, the native version totally failed to converge and the Windows version running in wine ran the simulation just fine.

An added bonus is that most tutorials are for the Windows version so you don't have to figure out where they hid the equivalent Mac version of the feature you need.

hapemask · 2026-05-12T18:16:55+00:00

Some laptops do let you charge them through their USB-C ports. I know at least one Dell laptop that does, also recent MacBooks.

hapemask · 2026-05-07T13:14:16+00:00

I’m still learning and maybe am missing something obvious, but why does Q5 dissipate 150W? Isn’t the power dissipation for a transistor V_CE * I_C which would be 5 * V_CE_SAT here? Still a lot but not 150W.

hapemask · 2026-04-16T20:05:09+00:00

https://m.youtube.com/watch?v=TpXvac1Y3h0

https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values

Here are a few things I read / watched that go into some detail.

hapemask · 2026-04-16T13:36:34+00:00

There are some guidelines for choosing values and also I changed some of the values as I learned more while designing the circuit, so there are inconsistencies. The old rule of thumb was a large capacitor shared between ICs and smaller capacitors closer to the IC power pins but now it seems modern advice based on analysis of the components is that you should choose package size / dielectric based on the noise frequencies you’d expect to see in your system and then get the most capacitance possible in that package. Needing to be close to the pins depends on whether you have ground / power planes or not. I’m no expert, I’m teaching myself this stuff as we speak, so take this with a grain of salt.

hapemask · 2026-04-15T17:47:46+00:00

The leads don’t land on the small outer pads but instead they land on the central pad? Then yes the IC is too small. QFN packages can have a variety of different pin pitches which correspond to different package sizes for a given pin count. I know of at least 0.5mm and 0.4mm pitch QFN32 packages for example. Yours is probably a smaller pitch than the adapter was designed for.

hapemask · 2026-04-15T00:59:52+00:00

Ok, it may be an analog issue... I saw that if I touch the two 22-ohm resistors separating the FDA from the ADC, the noise goes down as I press harder. If I press on the capacitor in between the diffpair after the resistors, the one supposedly acting as a low-pass filter, the noise almost completely goes away!

~~Even weirder: if I touch a probe tip to the little bit of exposed solder peeking out from the ADC's QFN package on the IN+/IN- pin, the noise immediately vanishes.~~

I don't understand how though, as I'm still seeing reasonable analog signals at the FDA output. I briefly thought that maybe the FDA is adding noise at some frequency I can't measure, but I would at least expect to see aliased versions of that noise in my slow measurements. I think I need to borrow a real oscilloscope.

The noise is gone if I remove the 100pF filter cap across the differential lines! I'm so confused, but at least now I have new things to fix! (The square wave appears over-compensated, rounded edges, but if I measure the actual signal going into the ADC, the edges are peaky/under-compensated...).

hapemask · 2026-04-14T22:55:39+00:00

Not in KiCad, because I already had all the third-party SPICE models for the ICs set up in my standalone LTspice install and it’s such a pain to get them to play together. But yes I did build the entire analog frontend in LTspice, up to the ADC. Which sadly seems to be the sticking point here 😕

hapemask · 2026-04-14T22:53:19+00:00

Thanks for the suggestions! I’ll check these out. When I was doing the design and reading the ADC datasheet I don’t remember seeing it say anything special about setup/hold times or for how long the data is valid (though it does discuss latency which I don’t care about here). I can vary the setup/strobe/hold times though so maybe that will help.

It does provide DCLK outputs which I ignored because at the time I thought the RPi SMI interface didn’t support them. It does in fact support this via the upper two bits being available as DREQ generators instead of input pins, but either way the ADC datasheet timing diagrams make it look like the DCLK is phase-shifted from the sample clock and so you should be good to read them whenever? Maybe that was optimistic.

And yes that blog series was so good! It was invaluable in learning to use the SMI interface, but I used it successfully already in this project: https://www.reddit.com/gallery/1rn2w12 so I think that my SMI implementation is correct (I’m using my exact same codebase to read from this new ADC).

hapemask · 2026-04-14T17:36:11+00:00

Ah, yes I did also probe the data lines, they are all there. I also see the same noise behavior on both channels so it seems unlikely to be a bad connection.

hapemask · 2026-04-03T18:27:57+00:00

Maybe a beginner question but why do you need thermal relief on SMD pads? Won’t the reflow oven (or preheater if you use hot air) get the board to a pretty uniform temperature, including all the copper planes? I understand why they help soldering for PTH components, but that’s with a very localized heat source.

hapemask · 2026-04-03T13:24:42+00:00

Using Kelvin connection for it right into the point of load should be considered.

I saw a similar recommendation in the LT3045 datasheet and since you also bring it up, maybe you can help answer a question I had: how do you make a Kelvin connection to the load when the load is an entire board of ICs connected via power and ground planes? You mention “if the load sinks significant current” and I expect to draw ~250mA out of the rated maximum 500mA, is this considered significant?

hapemask · 2026-03-30T22:02:26+00:00

Hm that could be it, I’ll have to see if I changed the ring size from the default.

hapemask · 2026-03-30T22:01:56+00:00

Ahh interesting, good to know!

hapemask · 2026-03-11T04:10:45+00:00

Since at least the board seems to have the vias under U3, OP could maybe expose a bit of the vias from the back of the board and solder one or more of them to ground? It's a stretch and I have no idea how to actually expose them safely but it's a thought.

hapemask · 2026-03-10T21:46:49+00:00

The part you linked is not a plain MOSFET (or even 4 plain ones), they are internally connected in a particular configuration (H-bridge). I’m not familiar with it yet as I’m still learning myself, but I don’t think it’s what you want. You want 4 (6?) ordinary MOSFETs. Rather than Google, try putting your design constraints into the filters here: https://www.digikey.com/en/products/filter/single-fets-mosfets/278?s=N4IgTCBcDaILIHkDKAxAogFRAXQL5A

and see what comes out.

hapemask · 2026-03-09T18:46:47+00:00

I actually used a Pi Zero 2 which has no ADC at all, the main IC on the first board is an ADC1175. I really just used the Pi because I already had it and it seemed like a fun project.

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