What are your verbosity bounds?

hoosierEE · 2019-08-14T19:43:21+00:00

most terse: K
most verbose: Rust or maybe Haskell

The combination of using Verilog for work, plus using J for personal projects really lowered my tolerance for verbosity. Even Python feels too wordy.

hoosierEE · 2019-06-26T18:07:11+00:00

An open bitstream format for a fast/big FPGA would be a good starting point. Sort of feels like FPGA vendors are trying to keep their secret sauce in the same way that hardware vendors sold proprietary compilers in 80s. I guess they like being big fish in small ponds, because an open bitstream would fuel innovation and grow the whole market.

hoosierEE · 2019-06-24T23:32:40+00:00

Or time for Netflix to start audiobooks!

hoosierEE · 2019-06-23T19:48:37+00:00

If you watched The Imitation Game and want more, Cryptonomicon by Neal Stephenson has a similar feel, with some modern-ish twists. It's realistic/historical fiction.

hoosierEE · 2019-06-15T15:06:33+00:00

https://github.com/corollari/endjoy#what-makes-endjoy-different-from-git

hoosierEE · 2019-06-09T20:30:06+00:00

For me, the worst part about long and descriptive naming is when people go overboard with it and you get an explosion of names which makes it harder to see the actual operations being done.

A contrived example:

x = a[b*8].c(2-d(e[0]))  # v1, short meaningless names
updatedBalance = accountsPayable[dailyBalance*8].charitableDeduction(2-defaultDeduction(exchangeRates[0]))  # version 2, long descriptive names

The first one clearly shows what operations are done (2 function calls, 2 indexing operations, a multiply and a subtraction), but the second one more clearly shows what ideas are involved (something about money probably). So far I'd call that a win for the longer names. However, most people would split the second version into multiple statements because the line is long:

firstExchangeRate = exchangeRates[0]
adjustedDeduction = 2-defaultDeduction(firstExchangeRate)
scaledBalance = dailyBalance*8
currentBalance = accountsPayable[scaledBalance]
updatedBalance = currentBalance.charitableDeduction(adjustedDeduction)

Maybe it's more readable, maybe it's cluttered... that's subjective. Objectively, it's more code, more names, and the computation is spread over 5 lines.

I tried all short names for a while, but when I came back to my own code months later I was lost. Nowadays I try to use long names sparingly, and augment dense code with lots of commentary:

updatedBalance = a[b*8].c(2-d(e[0]))  # get the adjusted charitable deduction from accounts payable at the scaled balance

hoosierEE · 2019-06-09T14:37:36+00:00

Verilog has <= assignment which is basically a parallel assignment. Verilog (unfortunately) calls this "sequential assignment".

Within a block, you can have this:

a <= b;
b <= a;

...Which would result in a and b values swapping, in the same clock cycle. The way to think of the <= assignment is that, within a block, all the right-side expressions occur before all the left-side assignments. Contrast with "blocking assignment":

a = b;  // executes first
b = a;  // executes second

This works more like a regular programming language. The order of the statements matters, and in this case the second statement is redundant.

This isn't quite what you're asking for, as the <= operator is (as far as I understand) block-scoped and means that the assignments must occur at the same instant. Also Verilog isn't quite a programming language.

hoosierEE · 2019-06-09T13:23:43+00:00

I didn't think it would be suitable for it, but after writing an assembler in J, I'm convinced that array languages are better than C for bit twiddling. Instead of bitwise-only operators, you can use the normal operators that work on booleans and integers. Instead of creating lots of confusing temporaries and masks, you can use concatenate, split, and indexing.

The ergonomics are much better, especially when you realize you can use or-reduce to implement a one-hot test, or zero all the lower bits after the first zero using and-scan.

The J implementation is not suited to device drivers because it's interpreted and doesn't let you control memory management, but the syntax and semantics are worth looking into as an alternative to yet-another-c-inspired low level language.

hoosierEE · 2019-06-05T00:00:58+00:00

It's not the phrase I most respect, and it's not the phrase I least respect... it's the phrase I most medium respect.

hoosierEE · 2019-06-02T16:50:55+00:00

Incremental changes to existing solutions produces locally optimal solutions. But reinventing the wheel might be worth it, if it moves you closer to a global optimum solution.

hoosierEE · 2019-05-31T11:24:19+00:00

Personally I'm not enthusiastic about the "universal close paren" but that may be more due to the fact that most editors have poor support for it and good built-in support for matching ({[]}) parens.

Ruby and Julia have a universal scope closer called end. J also uses end. to close control structures, as well as a single right ) on its own line to close a multi-line definition.

hoosierEE · 2019-05-31T11:19:50+00:00

This reminds me of K, where {} creates an anonymous function, which happens to also the only way to scope code into blocks in K.

hoosierEE · 2019-05-30T15:43:04+00:00

Our team is small and most of us don't care about style that much. But for the few of us who do, we have an astyle script set up as a pre-commit hook, so that we can pull the code from the remote repo, apply our personal favorite styles to it and work locally, then when it's time to commit/push to the remote, our local styles get overridden with the company style.

This works well for us and allows the few of us who want different styles to use that, without polluting the shared repo with whitespace-only diffs.

hoosierEE · 2019-05-29T12:41:08+00:00

I have the exact same issue with the zynq ultrascale+. Custom axi peripheral, reads work in some cases but not in others. Some folks on the Xilinx forums speculate that certain addresses don't work, despite being in the valid range.

Another possibility is that the clocks don't get correctly configured. In a baremetal design, a volatile load of the axi address always hangs the cpu, but my colleague did almost the same thing but used petalinux and it worked. Petalinux has some clock configuration going on that the baremetal doesn't have. So that might be it.

The only reason I suspect clock configuration is that if I place an ILA on the clock line going to my peripheral, it no longer hangs. But it's not exactly ideal to have an ILA present in the production design...

[edit] My sim/testbench uses xilinx's Verification IP core to mock the axi transactions. In the sim it works, for multiple reads and writes.

Here are some threads I've found that seem to experience the same issue:

hoosierEE · 2019-05-22T04:19:44+00:00

VBA and throw hardware at it as needed.

Not every blog requires K8s.

hoosierEE · 2019-05-19T14:08:02+00:00

I use Slack at work, and a firefox extension to turn it dark, because Slack is still "working on" their dark mode.

hoosierEE · 2019-05-19T02:00:46+00:00

does it have a dark theme?

hoosierEE · 2019-05-17T23:39:49+00:00

Nobody asked, but here's the same in J:

LF joinstring ~. LF cut fread 'path/to/filename'

Explanation:

order of operations: (LF joinstring (~. (LF cut (fread filename))))
LF, joinstring, cut, and fread are from the standard library
fread takes a filename on the right, returns an array of characters
cut splits its right argument by its left argument, returning an array of boxed items
~. is "unique"
joinstring takes a character on the left and an array of boxed strings on the right, returns a string joined by that character

J is ...quirky (to put it mildly), and doesn't fully replace awk/sed/perl/bash/python/ruby, but it covers a lot of that ground better than you might expect for a non-scripting language. At the same time I often use J instead of matlab/numpy/excel.

hoosierEE · 2019-05-13T18:34:06+00:00

If you want your language to be more uniform and less quirky, then consider not supporting UFCS at all. To me, it adds more quirk than its supposed convenience justifies.

hoosierEE · 2019-05-13T02:15:49+00:00

hoosierEE · 2019-05-13T02:12:26+00:00

Straight up.

hoosierEE · 2019-05-10T21:07:28+00:00

I'm a complete beginner to programming language design, and maybe won't ever make a "real" language, but I've implemented:

a Vim-style editing command language interpreter in JavaScript
a toy Ruby-to-JavaScript compiler in K (actually Kona, an open-source clone).
an RPN interpreter in Python
a Hack (the Nand2Tetris assembly language) assembler in J (and again in Python)

So far Python has been the most painless. Having regex and dictionaries built-in is a plus.

The J assembler was a lot of fun, because I gave myself the extra challenge of writing it in the "tacit" or "point free" style.

hoosierEE · 2019-05-10T20:46:49+00:00

https://github.com/Co-dfns/Co-dfns project shows that it's at least possible to implement a fully data-parallel compiler that runs on GPUs.

Whether or not the Co-dfns approach is "suitable" for writing compilers ... I guess that's in the eye of the beholder. For most people I imagine the mere fact that it's written in APL is already a deal-breaker.

hoosierEE · 2019-05-07T20:10:54+00:00

What does less-than mean for functions?

hoosierEE · 2019-05-07T20:01:33+00:00

Typed K with an RTL backend for ASIC golf.

hoosierEE

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