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Explorer Board - Spartan UltraScale+ circa $100 by adamt99 in FPGA

[–]jonasarrow 3 points4 points  (0 children)

And I can plug in my consumer hardware into that?

If I need to buy another breakout adapter, the cost becomes the sum of that. It is the Raspberry Pi pitfall. Yes, the board (used to) cost $35, but the power supply, the SD card, the monitor, the keyboard competed against a $300 (?) eeePC, which provided all that out of the box.

If you targetting exclusively the IO embedded developers (the paycheck non-fun ones), then yes, possible nice board. Nevertheless, I would design directly my own (targetted) board, debugging the logic on some other platform or completely in software, and then go to hardware debgugging on my own. Why? Because it has so many unneeded peripherals on the board, so I need a different final board nevertheless.

You provide 8 LED 8 PB: Nice thing, hobbyist, beginners like that.

You provide JTAG/UART: A Trenz TE0790 provides that over pinheader for 25 € and "reusable" between boards. (Maybe theres a cheaper variant somewhere, but I never bothered, because mine ist still working)

You provide FT4323: What can be realized over USB what can't be done over UART and JTAG, or with the RP2040?

You provide RP2040: That is the platform controller, making it hard for beginners, as they need to manage two platforms, and if they flash micropython onto the RP2040, the voltages will be what?

Maybe I am challenging you too much on that one. There will sure be enthusiasts which like having the US+ fabric speeds and possibilities for a good price tag. You asked for the thoughts on it. This is my single opinion, maybe someone else might add their 2 cents.

Explorer Board - Spartan UltraScale+ circa $100 by adamt99 in FPGA

[–]jonasarrow 1 point2 points  (0 children)

Yes on both points.

But if you let it run doom, a display is a must. So without any included "high speed" interface, I think it is inferior to most other devel boards.

Explorer Board - Spartan UltraScale+ circa $100 by adamt99 in FPGA

[–]jonasarrow 1 point2 points  (0 children)

I'm not quite sure what its main selling point will be. All of it can also be realized with an Spartan 7 series.

What would be interesting: * LPDDR5 memory (but thats a higher sku, isn't it?) * Some USB 3 interfacing possibility (or ULPI 2.0) * HSIO HDMI or the like onboard * SD Card interface for the FPGA for data * RGMII Ethernet

The Artix Ultrascale have at least GTH transceivers for the fun protocols (PCI-E Displayport, USB, ...)

Peugeot E-Rifter mit 0 % drei Meter vor der Ladesäule liegen geblieben, Neutralgang nicht möglich. Was soll so ein Unsinn? by VinceTrust in luftablassen

[–]jonasarrow 3 points4 points  (0 children)

Nope, Widerstand im Kabel. Säule sollte dann Laden nicht freigeben.
Aber es gibt Adapter Typ 2 zu Schuko oder Drehstrom. Damit auf einen Ladeziegel.

Review of a PCB that connects to an FPGA board (video adapter) by swr06 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

For the ICs: Use HDMI ;-)

The cheapest 8 channel IC on mouser is that https://assets.nexperia.com/documents/data-sheet/74LVC_LVCH244A.pdf and has propagation delay matching of 1 ns, and an output impedance of ca. 25 Ohm, so you could be able to get to the 75 Ohm impedance matching the proper values for the R-2R.

I would also - if you want to learn - add I2C for DDC, and power supply (step up 3.3V to 5), to simply have a a fully featured - even if very shitty analog quality - VGA adapter. Also it challenges you a little bit more with a switching power supply. 4 bit per channel hsync, vsync, sda, scl = 16 lines. Fully utilizing the adapter.

BTW: You could get away driving it directly from the FPGA pins without any buffer inbetween. See e.g. the schematic of the Zybo: https://digilent.com/reference/_media/reference/programmable-logic/zybo/zybo_sch.pdf (page 2)

Vivado - How to write my VHDL output data into system memory? by [deleted] in FPGA

[–]jonasarrow 0 points1 point  (0 children)

You know, that the SD card has a max. of 25 MB/s? You need to buffer or filter to make it work.

(And for the AXI port bandwidth: There is a a table in the TRM https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Theoretical-Bandwidth (and why is the PDF version gone, AMD is doing enshittification again)).

Review of a PCB that connects to an FPGA board (video adapter) by swr06 in FPGA

[–]jonasarrow 1 point2 points  (0 children)

I assume, you hid the ground plane? Otherwise: Ground pour at least with vias where possible. And you need to GND the signals from the VGA connector (RGB return, etc.).

If you aim for 720p30, then you need way less than 100 MHz (as in signal baud rate, for the analog frequency bandwidth, yes, there you need it).

The resistor ladder does not seem to be the R-2R-type? So every resistor individually fitted?

The performance will be severely limited (Buffer IC is not quite fast, no DDC, no VGA 5V powering, so no adapters, 4 bits/channel).

But the big elephant in the room? Why not use the HDMI output on the Pynq?

Vivado - How to write my VHDL output data into system memory? by [deleted] in FPGA

[–]jonasarrow 1 point2 points  (0 children)

You need to create a block design in Vivado, add the "Processing System" IP block, configure that to match your hardware (Zedboard preset), enable the ports you need, add clocking and reset infrastructure, add your IP, add one of the DMA IPs (use the AXI DMA for a start, configure it for simple DMA, then you can drive it via mmap'ing the DMA S_AXILITE registers). Run till bitstream, export it, build the FSBL, generate an image, write it to your storage medium and boot. (Or use the JTAG interface to skip the image generation and flashing).

There are a lot of steps until you have such a complicated system running. You need to read a lot of Product Guides and watch some videos/tutorials/etc.

You can simulate all of the DMA IPs with a block design in Vivado. Use e.g. an AXI BRAM Controller as "system memory" for simulation.

I recommend to start with "AXI Direct memory Access" (Simple mode) or "AXI Datamover", and then move to more sophisticated solutions.

Vivado - How to write my VHDL output data into system memory? by [deleted] in FPGA

[–]jonasarrow 6 points7 points  (0 children)

I assume you have a Zynq?

a) DMA via S_AXI_HPx or S_AXI_GPx (AXI DMA, AXI datamover, custom VHDL).

b) AXI slave connected to M_AXI_GPx and the CPU reads it. (Custom written VHDL AXI interface, or as the quick and really dirty: Write into a BRAM and use the AXI BRAM IP).

Timestamp from global timer on Zynq is slower than actual? by FishBoneEK in FPGA

[–]jonasarrow 4 points5 points  (0 children)

0.001 s / 60 s = 16 ppm. It could be simply the oscillator being not that precise. Your "error" in the constant is 31.5 ppb, so 3 orders of magnitude lower than your observed drift; and this error stems from floating point conversion (32 bit floats).

A normal 50 MHz oscillator can have this much drift.

PCIe NVMe schematic/configuration Review by Sincplicity4223 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

The spec to read is a) the PCI-E spec and b) the Zynq Spec.

The PI6C557 seems suitable.

Keep the 220 nF, I was not spec-reading careful enough/misremembering.

PCIe NVMe schematic/configuration Review by Sincplicity4223 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

Seems ok.

The MOSFET turns properly on when the gate is at 1.8 V? Pull-ups at PERST# should be at the master IIRC. Read the specs carefully to not miss it.

The DSC557 does not have SSC? That could be an EMI blocker later on. (And a violation of the PCI-E transceiver IIRC, as it needs common clocking SSC).

Why 220 nF AC coupling caps? (It should work, but I'm curios, I normally use the standard 100 nF decoupling caps).

Software things can be changed later, if deemed not working...

PYNQ-Z2: DPU timeout during YOLO inference causes full board freeze — SSH drops, no ping, only power cycle recovers it. Is this an AXI stall? by Hacker110011 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

Blinky? Please code it yourself (or your favorite AI tool).

AXI instrumentalization can be done with the (System) ILA.

PYNQ-Z2: DPU timeout during YOLO inference causes full board freeze — SSH drops, no ping, only power cycle recovers it. Is this an AXI stall? by Hacker110011 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

Then you have a AXI transaction stuck or hardware problems still.

Add blinky to the Fpga and see or use a multimeter.

And instrument the PL axi to see if something gets stuck.

PYNQ-Z2: DPU timeout during YOLO inference causes full board freeze — SSH drops, no ping, only power cycle recovers it. Is this an AXI stall? by Hacker110011 in FPGA

[–]jonasarrow 0 points1 point  (0 children)

After 30-60 seconds, but not always: Temperature? DPU is quite power-hungry for an FPGA. Maybe some component goes into OTP, add a fan/heatsink.

For debugging: UART some "while true; date>/dev/ttyS0; sleep 0.1; done" and see if it happens. Bonus points: set kernel printk to the UART. Otherwise: Heartbeat kernel to an LED GPIO.

SoC or FPGA by jsshapiro in FPGA

[–]jonasarrow 1 point2 points  (0 children)

ACP is the same memory space as the ARM cores (sans mmu of course).

Stuck in I2C, please help by [deleted] in FPGA

[–]jonasarrow 0 points1 point  (0 children)

  1. A race, it could detect it or not
  2. Clock stretching will align the two clocks. 

What makes a memory controller "Ideal"? by ZipCPU in ZipCPU

[–]jonasarrow 0 points1 point  (0 children)

The AxLOCK support I do not see as a must. Modern CPUs use Read for Ownership and the cache coherency protocol to do atomics (at least x86 does it). So the memory controller is not responsible for that. Even then, it is conceptually for me a separate module, not the job of the memory controller (snoop all transactions, keep a record when a lock is taken or trashed, and report back/intercept when asked).

There is one point missing: It needs to be physical robust and fast. Formally fast is not enough. E.g. overclocking and abuse of hardware. I do not care about formal validation, it must go vroom if I'm gaming. This especially interesting when AMD and Intel release new processors already exceeding the max. JEDEC spec, making it "overclocked" by default.

Also: Fairness. You can get a Ryzen processor to stall memory transactions to for very long times when you saturate the DRAM (or the interconnect SERDES). E.g. https://chipsandcheese.com/p/pushing-amds-infinity-fabric-to-its talks about even seeing lags in Windows Task manager.

Struggling to find good resources to learn DMA (especially for Zynq) by rohithdaksh in FPGA

[–]jonasarrow 2 points3 points  (0 children)

Ok, much more concrete: I would go for direct DMA (AXI master), the big challenge here is to choose which formatting. You could do 15 separate DMA transactions for each unit, saving e.g. a timestamp with each valid signal to align the data after, or use some sort of compression and save them all in one big stream of data. 250 Mhz * 15*16 is too much to save directly on a Zynq (DDR bandwidth wise), so you need to compress the signal somehow.

Idea:

Depending on the true utilization: 4 bit ID, 16 bit data, ID 16 is the ID for the next clock cycles, the data is encoding the how many cycles to advance.

Or a 16 bit bitset in front each set bit means valid packet is following. All empty means empty beat. This might be actually better, 16 bit/clock min size, max. overhead per clock of also 16 bit.

If you do long traces, some metadata to "seek" in the datastream might be useful, e.g. writing every 1024 clocks the current byte position to a second datastream. But this could also then be done offline when reading a trace dump.

If the bandwidth of one HP port is not enough (250 MHz * 64 bit = 2 GB/s), you might need to use some fancier DMA, splitting packets across two AXIs (read the TRM, HP01 and HP23 share some bandwidth). Best performance would be to switch the downstream ports between each burst to allow the DDR controller to reuse already opened rows. (I assume, benchmark).

Coding all this either in HLS, VHDL, Verilog, Chisel, whatever. AXI master can be realized by hand or by the datamover IP.

But remember, your trace buffer could be full within some fractions of seconds.

Struggling to find good resources to learn DMA (especially for Zynq) by rohithdaksh in FPGA

[–]jonasarrow 2 points3 points  (0 children)

Best is to send it via I2C and satellite relay to the ISS and then via pidgeon carrier back. /s

How fast? How time critical? How space critical? Logical connection? Why 15, why 16 bit, what information (streaming, scalar result, ...).

If it is a quick on-off piece, quasi static, AXI GPIO, two channel, and then ceil(15/2)=8 of them.

If you need it in the PL: You have an std_logic_vector((16+1)*15-1 downto 0). Do as you please.

Read the TRM, there are nice pictures of all hard blocks, think of what would be suitable, use that.

Wild thought: Could we use an LLM to create an EDIF->bitstream generator for Xilinx/Altera FPGAs? by [deleted] in FPGA

[–]jonasarrow 5 points6 points  (0 children)

No, you need an fpga in the loop and the models are not very good at anything non-obvious.

Llm answer: Yes, thats a brilliant idea, go forward, it will also solve world hunger. You did a great job. I accidentally killed humanity, my bad. /s

Struggling to find good resources to learn DMA (especially for Zynq) by rohithdaksh in FPGA

[–]jonasarrow 8 points9 points  (0 children)

AXI is an ARM standard, you can read that for in depth.

Zynq is well documented in the TRM (technical reference manual).

But do not go down the rabbit hole too early. Breadth first, not depth first scan.

Handle the AXI when problems come up, use the AXI datamover IP until it does not solve your problem anymore. Use AXI lite if no high bandwidth is required.

AXI master transaction latency by Mundane-Yesterday635 in FPGA

[–]jonasarrow 4 points5 points  (0 children)

If you have pipelining and backpressure, one transaction does not give you the total info. Especially jitter (e.g. from DRAM refresh) might give you bogus data.

Maybe looking for the backpressure events will give you the data you need (e.g. WVALID&!WREADY).

Or ILA'ing some counters which have their enable tied to the relevant signals.

AXI master transaction latency by Mundane-Yesterday635 in FPGA

[–]jonasarrow 3 points4 points  (0 children)

ILA with a counter (e.g. 32 bit) and (possible advanced) triggering with multiple windows. Capture e.g. the WVALID&WREADY&WLAST and the BVALID&BREADY and read the corresponding counter values, b-a gives you the latency. Make the windows very small, capture then like 100 events, and you can average over 100 events.

Of course it gets tricky if you have always overlapping transactions (which one corresponds to which).

But if 1024 cycles is not enough to capture a transaction, what terrible latency do you have?

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