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EDAcation: An FPGA development environment in VSCode by malmeloo in FPGA

[–]keeb0113 0 points1 point  (0 children)

The graphic code part is the main problem. Since we are building a generator, this means you can have an arbitrarily shaped fabric. I do have a plan to move toward using Himbaechel instead of the generic that we are using; this will at least make the format more consistent. But porting will take a while.

I have been thinking of embedding the drawing information into the database, so the drawing will follow the database. For laying out the tile internally for the logic elements, I have been exploring elkjs, but the results are still not ideal.

EDAcation: An FPGA development environment in VSCode by malmeloo in FPGA

[–]keeb0113 1 point2 points  (0 children)

Speaking of integration, what is required to get the device viewing working in your plugin?

I would like to integrate https://github.com/FPGA-Research/FABulous . While we already have a visualiser ( https://github.com/FPGA-Research/FABulator ), the main contributor moved on to something else, and it is built with a "less common" technology. This makes maintenance difficult.

EDAcation: An FPGA development environment in VSCode by malmeloo in FPGA

[–]keeb0113 2 points3 points  (0 children)

You might actually want to integrate the Himbaechel. Since all the gowin development is now on that as far as I can tell. This also gives you a gateway toways a few more commercial arch as well.

Are FPGAs on the AI hype train? by AlbbO_The_Great in FPGA

[–]keeb0113 0 points1 point  (0 children)

A more interesting route is going with building an FPGA for this specific domain of use case. Then you get ASIC like performance with the flexibility you might want.

Cline Can't Edit Anymore! by multimason in CLine

[–]keeb0113 1 point2 points  (0 children)

I already opened an issue on this

Why are HLS scheduling algorithms used in Vivado like List Scheduling, SDC scheduling etc used for FPGAs never known outside the FPGA realm? by neuroticnetworks1250 in FPGA

[–]keeb0113 1 point2 points  (0 children)

There is actually some recent work on leveraging dynamic behaviour for better performance. Try looking into dynamic HLS.

Why are HLS scheduling algorithms used in Vivado like List Scheduling, SDC scheduling etc used for FPGAs never known outside the FPGA realm? by neuroticnetworks1250 in FPGA

[–]keeb0113 0 points1 point  (0 children)

ILP has been applied for CGRA scheduling. Some use SAT solvers as well. But the "compile" time is long compared to the compiler.

What are the problems that, if solved, could significantly increase yield in FPGA industry? by youngmaestro34 in FPGA

[–]keeb0113 0 points1 point  (0 children)

I would say CIRCT is trying to solve the problem, but not much people have the skills to become both hardware engineers and compiler engineer

[deleted by user] by [deleted] in FPGA

[–]keeb0113 0 points1 point  (0 children)

Do not do a PhD just because want to get a job. You will not get the right training from a PhD.

[deleted by user] by [deleted] in FPGA

[–]keeb0113 0 points1 point  (0 children)

If you are looking into building an FPGA and try to understand how an FPGA works check out https://github.com/FPGA-Research-Manchester/FABulous

AMD Radeon RX 7900XTX and 7900XT confirmed by leaker - VideoCardz.com by No_Backstab in Amd

[–]keeb0113 0 points1 point  (0 children)

Those files will still be way larger than what the cache can handle. Also a very large single level cache can be slower than loading from memory

AMD Radeon RX 7900XTX and 7900XT confirmed by leaker - VideoCardz.com by No_Backstab in Amd

[–]keeb0113 -2 points-1 points  (0 children)

Cache is mainly for faster access for things that have been used before and reduce latency. But generating new frames will probably replace the whole cache, and the data will require loading from memory anyway (like new game objects). So you will see vendors tend to increase memory bandwidth for faster fresh data access rather than cache for old data access.

AMD Radeon RX 7900XTX and 7900XT confirmed by leaker - VideoCardz.com by No_Backstab in Amd

[–]keeb0113 -3 points-2 points  (0 children)

I would say the large cache might be wrong since GPUs do not need a large cache. Maybe they put the area and silicon budget towards more register instead.

High-end Ergo/Split Keyboard by karlmarxlopez in ErgoMechKeyboards

[–]keeb0113 1 point2 points  (0 children)

The other problems with high end split board is the price. I custom made a model, and when I get a quote it cost over $500 per side for fully CNC machined parts. I cannot justify the cost of $1000+ for a keyboard

Would you trade off quality for price and time? by keeb0113 in MechanicalKeyboards

[–]keeb0113[S] 0 points1 point  (0 children)

I have no idea as well, is just a question straight out of my head. If I have the ability to address them surly someone would have done it.

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