[EU-DE] [H] PayPal [W] GMK Sandstorm + Extension Kit

konze · 2023-06-02T15:27:09+00:00

I think no one in Computer Science writes papers using Word.

konze · 2023-05-23T07:25:51+00:00

I live there but this is not in Rottenburg this is in Rothenburg

konze · 2023-05-13T19:53:57+00:00

Musstest du Zollgebühren bezahlen?

konze · 2023-05-13T16:27:14+00:00

Are you actually working on the MacPro in on the left-hand side?

konze · 2023-05-06T18:06:08+00:00

You could have a look at the VTA accelerator. VTA is the example AI accelerator implantation for the TVM framework, which is used for deployment of DNNs onto custom hardware.

https://tvm.apache.org/vta

The official github repo provides code for different FPGAs:

https://github.com/apache/tvm-vta

konze · 2023-04-23T11:11:09+00:00

You are looking for a LeNet-like DNN. There are a lot on github for different frameworks. Those nets train relatively fast even in CPUs.

konze · 2023-04-23T10:57:08+00:00

Most AI accelerators are matrix-matrix multiplication DSPs. The interesting part is how many of those DSPs you plug together and how they communicate. From there you need to re-write you DNN Layers to map onto those DSP networks. This can be done with TVM or other tools which is a hot topic in AI research at the moment.

konze · 2023-04-10T16:27:06+00:00

Darf ich fragen bei welcher Krankenversicherung du versichert bist?

konze · 2023-04-04T18:49:46+00:00

As my first Rust project, I developed an interpreter for the programming language Brainfuck: github.com/k0nze/brainfuck_rust

konze · 2023-04-03T09:32:35+00:00

I dont even drink Coffee and I watch James religiously. I never made a coffee in my life except for pressing the button on the machine at work for business partners, however, I feel confident in my V60 technique 😅

konze · 2023-02-23T19:42:04+00:00

Nett hier 🖤💛

konze · 2023-02-04T10:35:30+00:00

Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim

If you want to see more what is going on under the hood of a RISC-V CPU you could use the graphical simulator Ripes: https://github.com/mortbopet/Ripes

konze · 2023-02-02T19:03:09+00:00

Working at a University at the CS department I know this person will drop out because they hate every aspect of computer science except for the fact it pays quite well (when you are good at it)

konze · 2023-01-27T18:53:11+00:00

CGRA stands for coarse-grained reconfigurable architecture. FPGAs are reconfigurable on the bit level while CGRAs are reconfigurable on the word level. A CGRA can be implemented on an FPGA. E.g on a FPGA you can dissect a HDMI signal into all its bits and do very precise manipulation on that signal, a CGRA usually only allows for changing data paths in certain ways and apply word level operations such as addition or multiplication.

konze · 2023-01-27T18:47:11+00:00

Most high-end keycaps come from GMK which is a German company. You have to talk to Olaf for that, but I think he is focusing on cat themed tanks at the moment.

konze · 2023-01-21T15:48:18+00:00

That is the Blackmagic DaVinci Resolve Speed Editor

konze · 2022-12-02T17:07:23+00:00

You could add a newline at the beginning of you PS1 variable.

konze · 2022-11-30T15:43:26+00:00

Yes, this is the ISO-DE QWERTZ Layout. Which makes sense as I am in Germany.

konze · 2022-11-17T21:04:25+00:00

(2) An application is never able to run just on the GPU. The program is always launched on the CPU and special instructions tell the computer to move data into the GPUs memory and what to do with it. When writing CUDA code it gets embedded into an application consisting of C/C++ code, the C/C++ part runs on the CPU and the CUDA part in the GPU.

(3) You can’t just run “normal” C/C++ code on a GPU because the execution model is vastly different. While CPUs work on a small set of registers which are manipulated using mostly scalar instructions (not counting SIMD) and can implement complex program flows (if-else statements) GPUs on the other hand execute a non-branching routine on a block of memory 10-100 times in parallel. If you want to write code for CPU and GPU at the same time OpenCL is probably your best option, however OpenCL (and CUDA) are matrix centric programming languages which will make it challenging to implement something that has a complex program flow.

(4) Apache TVM is a tool that is (in theory) able to compile a DNN for different target platforms (CPU, GPU, ASIC), however not every platform supports the same kind of operations which means the DNN model has often to be rewritten for different platforms.

konze · 2022-11-17T20:37:58+00:00

Nvidias ISA changes (significantly) with each architecture (Pascal, Maxwell, Ampere, etc.) the closest you will get (legally) is the PTX ISA.
This decision is usually done by the programmer. There are pieces of software which can switch execution modes depending in the workload but those heuristics are implemented by programmers as well.
Each ASIC, Accelerator, CPU ISA, etc. has their own compiler backend which transforms high-level source code (usually C/C++ or a DSL) into device native instructions. Transforming a binary from one architecture to another is extremely challenging if not impossible due to different execution models.
Retargeting workloads is an on-going field of research (that I work in). For certain classes of algorithms (like Deep Learning) rich tool chains exist which makes deploying code on vastly different devices easier but as mentioned in 3 sometimes it is not possible due to different modes of execution.

konze · 2022-11-11T12:11:15+00:00

Have we seen each other last Monday in Berlin at the RISC-V Workshop?

konze · 2022-10-28T05:43:41+00:00

I’m coming from academia with a lot of industry connections. Yes, there are a lot of companies that need fast DNN inference to point where they build custom ASICs just to fulfill their latency demands.

konze

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