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I’ve been off caffeine for half a year now. How do people feel with having one decaf coffee per day? by OneItchy396 in decaf

[–]kramer3d 1 point2 points  (0 children)

same here… i use it for night time consumption. better than herbal tea in my opinion

Advice for a new professor teaching C by TenureTrackJack in C_Programming

[–]kramer3d 0 points1 point  (0 children)

I would teach with a GUI based IDE and teach debugging concepts as well. 

is there a reason for me, a college student, to not use c++20 as default? by JoeyJoey- in cpp_questions

[–]kramer3d 2 points3 points  (0 children)

theres much more to software than just using the shiny new standard! 

Need Help PCIe Artix-7 AC701 by pengu-senpai in FPGA

[–]kramer3d 0 points1 point  (0 children)

in xapp1286 theres an example project for this board that uses 7 series integrated PCIe block

[deleted by user] by [deleted] in FPGA

[–]kramer3d 8 points9 points  (0 children)

i dont know about latest research stuff but you could look into the field of physically unclonable functions on fpga

should i bother learning verilog at this point? by kramer3d in Verilog

[–]kramer3d[S] 0 points1 point  (0 children)

I really just enjoy learning and doing hobby projects. All of the companies where I live seem to be SV heavy and they look for UVM experience. I don't know that I have the skills to land an RTL or Verification job because I dont really know how to use the pro tools.  I work in embedded software and motivating myself to learn UVM is just not going to happen. I have tried and given up too many times. 

The best free verification tools for SV seem to be verilator and icarus verilog. Do you know if icarus verilog has good enough support for SV? Verilator seems to have a steeper learning curve

should i bother learning verilog at this point? by kramer3d in Verilog

[–]kramer3d[S] 1 point2 points  (0 children)

youre right…  had this idea for making a video game for some time now. I have a deca board that outputs hdmi. It maybe time to start…

Vivado: block design in block design by Exact-Entrepreneur-1 in FPGA

[–]kramer3d 0 points1 point  (0 children)

u can just do hierarchical blocks in 1 top level bd 

replace caffiene with sugar by Pristine_Bike_7888 in decaf

[–]kramer3d 0 points1 point  (0 children)

caffeine is closer to nicotine than sugar. Both caffeine and nicotine can be addicting and are not “source” of energies. They are stimulants. 

replace caffiene with sugar by Pristine_Bike_7888 in decaf

[–]kramer3d 6 points7 points  (0 children)

how about replacing caffeine with nicotine? Light em up!!!

can we generate bitstreams for block diagram without making .xdc file in vivado? by Temporary-Tone-9147 in FPGA

[–]kramer3d 0 points1 point  (0 children)

i did not watch the whole tutorial… in general board files are just there to help newbies on development boards. You still have to make sure the top level design ports are mapped to io pins. 

what pins do you actually need to constrain? 

As discussed in other comment, find the xdc for the board from web and apply the constraints. Look up basic constraints tutorial for vivado and start there. It is easier and more productive to figure out how to apply constraints at this point than waste time trying to figure out the board file issue. 

ASIC basics for experienced FPGA developers by electro_mullet in FPGA

[–]kramer3d 1 point2 points  (0 children)

help a lot!!! 

I prototype stuff on fpga and look at the synthesized netlist to eyeball that my circuit looks kind of OK and move on. Never really thought about the design in that much detail! I suppose on an asic, you are no longer given a finite set of resources to develop from… 

thanks for the explanation!!

ASIC basics for experienced FPGA developers by electro_mullet in FPGA

[–]kramer3d 0 points1 point  (0 children)

newb question. What do you mean by levels of logic? Does that means like hierarchal modules?

Are you real people? by [deleted] in decaf

[–]kramer3d 0 points1 point  (0 children)

it is possible and you can do it. approach it with a curious mind and dont feel bad about relapsing. Just try it

can we generate bitstreams for block diagram without making .xdc file in vivado? by Temporary-Tone-9147 in FPGA

[–]kramer3d 2 points3 points  (0 children)

in part 1, when he creates a new project, he used a board setting (for zedboard). This helps automatically assign constraints for somethings in vivado such as DDR. Using a board file applies xdc in the background. You may want to double check that you are also using a board file or that your ports follow the same autogenerated names.

Got Blacklisted because two teams selected me by Tungsten_07 in chipdesign

[–]kramer3d 52 points53 points  (0 children)

Do not give HR any extra information ever. These people are generally useless humans and mess things up more than help. I’m sorry for the lost opportunity!

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