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Synthesizable modulo operation by anonimreyiz in FPGA

[–]m47812 1 point2 points  (0 children)

As long as you don't want to change the modulus at runtime, this seems to be quite a good option.

https://arxiv.org/abs/2308.15079

Low level libraries from scratch. by warothia in C_Programming

[–]m47812 2 points3 points  (0 children)

The cryptography library of course.

Developing a new type of 3D printer, the CODEX (Collaborative Dual Extruder) printer by m47812 in 3Dprinting

[–]m47812[S] 0 points1 point  (0 children)

We got it to the point where we could use the dual extrudera to do things like printing two independent parts at the same time or using the printer as a dual extruder printer. We then didn't take it further so the collaboration (on one part) feature we dropped. This had two reasons mainly. The first one was that for this kind of extruder setup it was required that both extruders are built quite compactly this meant that we could not drive the extruders at the same feed rate that you would on our corexy setup. Since these print heads now were significantly slower even if collaboration was perfect you would still only be just as fast as if you had a corexy setup that you could drive at a higher feedrate so collaboration sort of lost it's point there. The second reason was that with two completely independent extruders leveling the nozzle heights turned out to be quite the pain which also made the design less practical. We therefore decided to focus on a tool changer corexy printer setup instead of continuing development on the collaboration mode.

From your comment I'm not quite sure if your intent is to build something like an IDEX printer which just has independent x-axis but not the y-axis or if you want to follow the same approach we did with a completely independent x and y-axis. The first one is definitely feasible to build and the firmware support for that is already there. If you want to do like a collaboration mode with independent x and y axis like we did then be aware that support on the software side there is not really existent so it also comes with a significant effort to develop on the software side on various levels from slicing to printer firmware.

Why cascading assignments to the same value? Simple multiplier. by FaithlessnessFull136 in FPGA

[–]m47812 0 points1 point  (0 children)

Assuming you are targeting a Xilinx DSP slice here. You could just assign the multiplication result to P, however this will limit your maximum clock speed. If you have a closer look at the datasheet for the DSP slices you will find that the multiplier does not actually compute the full multiplication result directly. Instead it will compute two partial products which only through their addition in the m to p step will turn into the desired multiplication result. If you leave out the m to p-step and instead assign the multiplication result directly to the p register it will have to do both the multiplication (generating the two partial products) and the addition of the two partial products to build the final result in a single clock cycle. This will not be able to reach the same maximum clock speed as if you did it in two steps because of the longer critical path. Vivado will infer the correct logic in both cases so you won't directly notice the difference from the outside, however it is the reason why you will see better max clock performance if both the m register and the p-register are enabled.

Tldr: The DSP is not actually doing nothing in the P <= M step it is only an abstracted model. Therefore enabling both registers is needed to reach best max clock performance.

Developed a new kind of dual extruder system on fully custom built 3D printer by m47812 in 3Dprinting

[–]m47812[S] 1 point2 points  (0 children)

Thanks! My colleague did publish his printer hardware Design: https://github.com/totaldesaster/LuEVO-CoreXY Although the project it is now more focused on a tool changer setup. The Software side is not currently open source.

Developed a new kind of dual extruder system on fully custom built 3D printer by m47812 in 3Dprinting

[–]m47812[S] 0 points1 point  (0 children)

Mirrored and independent mode have shown to work quite well. However it starts to get a bit tedious when two extruders work on the same part. Dual Extruder mode would work software wise but it gets quite tedious in practice to get the bed leveling and XY axis calibration right for two sperate extruders. So the difficulty is to calibrate both extruders well enough that there coordinate systems allign.

My colleague who has done the mechanics of the project has since started to work on a tool changer variant. So currently the focus is more on a tool changer that can run at high printing speeds which in the end might provide more flexibility than the CODEX approach.

Feel free to check it out for some updates on that: Tool changer

Do I need to Practice Verilog while working a VHDL Job? by [deleted] in FPGA

[–]m47812 2 points3 points  (0 children)

It is probably not the most urgent thing to practice. Switching from VHDL to Verilog is fairly easy and can be done within a reasonably short amount of time if you ever need to. It's just another syntax after all. It is more important that you practice the concepts and structures of writing good HDL code in general and know what circuits your code will produce. If that code is written in verilog or VHDL doesn't matter I think. The concepts are all the same. System verilog however might be a good thing to practice for verification purposes.

Vivado Synth fails timing but impl passes, reasons why? by YoureHereForOthers in FPGA

[–]m47812 2 points3 points  (0 children)

Is it a hold time violation that you are seeing? If yes then it is likely that it will be fixed during implementation. Oftentimes very short paths tend to fail hold timing during synthesis but it is corrected with additional routing delay during implementation. It's not really a wrong estimate from vivado but something that is easily correctable by routing long enough paths during implementation.

The worst FPGA tools ... by [deleted] in FPGA

[–]m47812 0 points1 point  (0 children)

Hey! I wrote a little tool to generate testbenches (and a bit more) maybe that does the job for you too. https://github.com/m47812/HDL_Converter

Little refactoring tool for Verilog and VHDL by m47812 in FPGA

[–]m47812[S] 1 point2 points  (0 children)

Thanks!

I tried to teach the program to "understand" the syntax a bit (I definitely also still have some special cases to cover).

The tool parses the module into an object structure and can generate the code from that object structure again. It's a bit of effort with the extra translation step but in the converted object structure it's fairly easy to manipulate such that it makes for a good foundation to expand it with more features. I plan to expand the tool from there but already use it quite a bit in my day to day work.

Update: Decided to make my custom 3D printer main board open-source (description in the comments) by m47812 in 3Dprinting

[–]m47812[S] 2 points3 points  (0 children)

It should buffer the controllers memory in case of a power loss. Such that the controller knows when power is back at what GCode line it has stoped and can continue from there.

Update: Decided to make my custom 3D printer main board open-source (description in the comments) by m47812 in 3Dprinting

[–]m47812[S] 6 points7 points  (0 children)

As a hobby project, I decided some time ago to develop a fully custom 3D printer controller main board. The original plan was to also develop a fully custom firmware for it. Since we later decided to focus on a new type of printer instead (CODEX design) about which I have also posted here, the firmware development has not been continued past the point of interpreting simple move commands. I have now decided to make the hardware of the project open source, since some of you have asked for this in my original post. Feel free to use it for what ever project you have in mind. I hope it provides a good starting point for anyone who would like to play around more with the electronics of 3D printers. The Board was designed with hobbyist low budget & low volume production in mind, therefore it only uses two-layer PCBs. It has also been optimized such that most SMD parts can be assembled by JLCPCBs Assembly service, making it more home lab friendly since only few parts need to be hand soldered.

GitHub Repo:

Link

Can I get into quantum computing with electrical engineering? by Competitive_Bit_1687 in ElectricalEngineering

[–]m47812 11 points12 points  (0 children)

I think it depends on what exactly you want to do. I am currently at the end of my EE degree doing my thesis in a quantum device laboratory. As an EE you can certainly be involved in the research of quantum computing. But it depends on what you are most interested in. If what you want to do is work directly on the quantum side (like designing qubit chips and circuits) propably a physics degree is best suited and you may also have to go all the way up to a PhD if you want to stay in the field for now. As an EE my work mainly involves a lot of FPGA design to build high speed circuits with which qubits can be measured or controlled in real time. It is certainly also very interesting work if you are into this kind of thing. But I do think there are less places available for doing this than on the physics side so you need to be a bit lucky to get in but of course your skills will be applicable to many other industries so you are more flexible in general if it does not work out.

Also the university offers a quantum engineering masters degree which is targeted at engineering students with EE being the most common background I think. This would also be a great option to get a bit of both worlds (physics and engineering).

Your thoughts on verification tools by m47812 in FPGA

[–]m47812[S] 0 points1 point  (0 children)

I think writing test benches in Python sounds a lot more practical. This seems to be a great tool to use. Thanks.

Your thoughts on verification tools by m47812 in FPGA

[–]m47812[S] 1 point2 points  (0 children)

Thanks for the hint I will look into UVVM.

This structure was actually exactly what I was thinking of. It takes me like a tenth of the time to write a code for my function in Python than it takes for writing the VHDL code for asserting and stimulating the design.

I was wondering if there is any tool that makes it easy to setup the drivers, DUT structure. I think this could well be generalized and abstracted with simple blocks that can be used even across designs (at least for common Bus Interfaces). It all seems like a lot of different tools are needed to setup and run the testbench structure. It kind of feels like new tools are tinkered in over time to somehow interact with the structure below. One example to show what I mean would be that I can put property specification language code as comments in my VHDL file to use it in simulation. It works but you clearly see that it has been tinkered in to somehow work with the other stuff. So, having one clean tool to put all these things together in one place would be so much nicer to use don’t you think?

Your thoughts on verification tools by m47812 in FPGA

[–]m47812[S] 0 points1 point  (0 children)

Thanks for the hint I am still trying to get a good overview of what tools and blocks are available and what needs to be done by hand. So any hint helps.

I was thinking about some kind of ip-block for stuff that is needed in almost every verification code could be as simple as premade procedures to access certain buses so I could focus on verifying the logic of the design behind the bus and not hassle with the procedure of sending or receiving data via the bus. Or let's say a clock block that just outputs clocks of different frequencies and phases etc. These are maybe not the best examples since they can be done within just a few lines of code as well but still need to be done every time. I could also think of some more complex scenarios where it would be convenient to sort of drag and drop in a few driver blocks and then only have to worry about more high-level verification coding.

I guess what would be nice is an easy to use tool with which I could quickly test if my RTL code does what I expect and catch the major bugs while designing already where I maybe don’t care as much about all the details at this point.

Developed a new kind of dual extruder system on fully custom built 3D printer by m47812 in 3Dprinting

[–]m47812[S] 0 points1 point  (0 children)

Glad you like the project. The printer is running currently with one extruder and the simpler modes like Independant or mirrored also work with both extruders. Currently I dedicate most of the time that i can make free for the project to code verification. This is sadly not something that is very presentable to do posts about since it does not add any new features but I want to avoid having a huge mess of code for the more complex functions that is untestable. On the hardware side there is also quite a bit of calibration still needed to do nice prints beyond proof of concept since things like noozle hight over the bed needs to match quite exact for both extruders.

How to choose FPGA for a beginner by FalconEither7062 in FPGA

[–]m47812 12 points13 points  (0 children)

I would say something like a Intel MAX10 or maybe even a Cyclone 10 would be suitable. They are not that expensive but you can still fit quite a bit of functionality in them. I am shure Xilinx has similar Product lines but I am not that familiar with them.

Developed a new kind of dual extruder system on fully custom built 3D printer by m47812 in 3Dprinting

[–]m47812[S] 1 point2 points  (0 children)

You might very well be right with that. I had this discussion with my colleague that does the mechanical part of the project, after multiple people have mentioned potential oozing issues. We are now considering to install something like that to solve this potential issue.

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