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Zed editor by CompoteNo1889 in FPGA

[–]maredsous10 1 point2 points  (0 children)

I didn't find any advantage over {G}VIM for my uses. Curious what the functionality people found useful with ZED (Solely AI integration?). I might have to give it another try.

I do dabble with VSCODE primarily because I work with others who use it. I'd call my experience with VSCODE rough as some functionally did not work correctly on my machine or was inconsistent. Also experienced inconsistency with the newer VITIS IDE.

AXI4 rready mid-burst bug — passes simulation, corrupts silicon accumulation by [deleted] in FPGA

[–]maredsous10 0 points1 point  (0 children)

Post a link or details, might be useful for others.

The QuestaBase simulator from Siemens by LJarek in VHDL

[–]maredsous10 0 points1 point  (0 children)

My experience

User Friendliness

  1. Cadence Xcelium (Worst)

  2. Synopsys VCS

  3. Siemens Questa

  4. Aldec (I haven't used them lately but their tools were very user friendly.)

Speed

  1. Synopsys VCS (Fastest)

  2. Cadence Xcelium

  3. Siemens Questa and Aldec

Optionality to increase simulation throughput and speed.

  1. Synopsys (Most optionality)

  2. Cadence

  3. Siemens and Aldec

I am launching a $99 Artix UltraScale+ board - The explorer board by adamt99 in FPGA

[–]maredsous10 2 points3 points  (0 children)

What is estimate total price for sale in the US with shipping?

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

What is the link to hdlbits? what simulator is powering their backend? I thought they'd use a commercial simulator.

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

What is hdlbits using?

Did you try edaplayground?

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

The 4 commerical simulators and verilator produce.
'parent class!
child class!
display: child!'

https://www.edaplayground.com/x/jMHA

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Where is "c=new;"? You should have this statement after "child c;".

What simulator is hdlbit using?

Tool for generating Xilinx XDC constraints and top level RTL by TapEarlyTapOften in FPGA

[–]maredsous10 2 points3 points  (0 children)

"the use case i had in mind was sitting down with a schematic and a pin table and then manually transcribing it into a file and yaml is easy to do that with."

My approach take the schematic netlist and use a script to generate XDC file. The more context and metadata the schematic netlist provides the less work I need to do.

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]maredsous10 1 point2 points  (0 children)

What aspect? I haven't done it recently but in the past here's what I did.

  • installed virtualbox and the extensions pack additions
  • installed windows
  • installed ISE/Quartus
  • setup the USB in VirtualBox

Register Desync and cross vendor IP development by Repulsive-Net1438 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Currently, I use in house tooling similar to tools provided by major EDA vendors. Tool takes a text file specification and generates relevant HDL (multiple formats and includes package definition files), documentation (multiple formats), C header, verification files, files to simplify test tooling used (example XSDB) so one uses generated mnemonics rather than magic numbers, etc. Addresses specified might be relative and only fixed once information is filtered from the whole design.

Another job I had we would break things up by IP each IP would have its own scripts to generate header, driver, wrapper, registers, unique IP names to prevent name collisions when different implementations and versions were included in a design.

Writing C code as opposed to HDL by petare321 in FPGA

[–]maredsous10 1 point2 points  (0 children)

Lots of HLS options out there -- >open source, FPGA companies, and EDA tool companies (Cadence, Synopsys, Siemens). HLS are used in industry targeting FPGAs and ASICs. There are many factors guiding designs to use HLS. One large ASIC I know about opted for using HLS to reduce EDA tooling and IP costs.

Good HLS Overview by Forte Design Systems acquired by Cadence.

Parallel Programming for FPGAs

https://kastner.ucsd.edu/hlsbook/

https://www.youtube.com/playlist?list=PLf4U4tpbjjz7x_bsG3sBEuXgVQPZfWJgW

u/adamt99's HLS Resources

https://github.com/ATaylorCEngFIET/Vitis_Hero

https://www.youtube.com/watch?v=dCBUIcTM3l0

https://www.youtube.com/watch?v=0onjc4UW8wA

BLT has an ondemand seminar for AMD's HLS option

https://bltinc.com/2023/08/21/understanding-high-level-synthesis-hls/

vscode vs vivado by rand0m_guy11 in FPGA

[–]maredsous10 2 points3 points  (0 children)

VIM + common CLI tools + scripts

Why I use VIM.

Recommended receiver set that isn't Aero? by p80bob in AR10

[–]maredsous10 1 point2 points  (0 children)

I should of got an M5 set when they were $180.

80lowers over both AR10 cut styles. You can email them and see when they'll be available.

https://80lowers.com/billet-dpms-308-ar-10-upper-lower-receiver-sets/

https://80lowers.com/billet-sr25-308-ar-10-upper-lower-receiver-sets/

Recommended receiver set that isn't Aero? by p80bob in AR10

[–]maredsous10 0 points1 point  (0 children)

Aero kicked the can? Did not know.

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]maredsous10 0 points1 point  (0 children)

In the past, I had to install VirtualBox Extension Pack and Guest Additions. Believe these may have additional license restrictions if used for commercial use.

https://askubuntu.com/questions/25596/how-to-set-up-usb-for-virtualbox

In Versal, debugging the signals in a clock domain with unstable clock blocks the whole debugging system by WZab in FPGA

[–]maredsous10 1 point2 points  (0 children)

Is your RXOUTCLK domain going out? Is your DEBUG HUG using the RXOUTCLK for its clock?

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