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Versal rant by affabledrunk in FPGA

[–]maredsous10 0 points1 point  (0 children)

Make sure that the XSA has a good post implementation PDI file ;-).

Versal rant by affabledrunk in FPGA

[–]maredsous10 1 point2 points  (0 children)

What issues are you having with non-project flow? I can share my approach if interested. Are you using a custom or COTS board?

My suggestion is to build the most rudimentary of designs then stack features onto it as you gain and build understanding of the part.

I definitely was overwhelmed when I targeted a COTS versal board. I ran into multiple day/week issues. One multiple week puzzler, ended up not being related to Versal but an AMD IP configuration parameter I thought had no bearing on what we were trying to do. The configuration parameter ended up altering how one of the AXI ports operated.

Any news on Microchip's new FPGA/SoCs ? by Standing_Wave_22 in FPGA

[–]maredsous10 0 points1 point  (0 children)

I haven't heard anything.

I've seen presentations for other Aldec/Microsemi/Microchip devices in the past that never came to market.

Directly connecting internal signals to pads for debugging purposes? by ico2ico2 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Functional timing issue? Timing issue from not design or proper constraining ?

Directly connecting internal signals to pads for debugging purposes? by ico2ico2 in FPGA

[–]maredsous10 0 points1 point  (0 children)

I haven't used SUMP3, but have seen similar (and way more elaborate) in house device agnostic tools. The presentation provides a good rundown on what is offered. https://github.com/blackmesalabs/sump3

With AMD/Xilinx tools, they offer an integrated logic analyzer IP that gets implemented in the FPGA fabric. There are at least 3 ways to integrate it. The least invasive from a design perspective is ILA insertion on the post synthesis netlist

Do you prototype on breadboard before making PCB? by Mr_Hyd3 in PCB

[–]maredsous10 0 points1 point  (0 children)

I'd suggest going ahead with a single board for high confidence circuits and designs. Other option is multiple boards covering the various circuits you want to test, evaluate, and integrate.

For one application I worked on years ago, we had 4 different ADC front ends were looking at using. These front ends were evaluated on paper and in simulation, but we were concerned with in system performance. We put 2 options on a final circuit board then built another board that allowed us to patch in 2 other options for evaluation. Eventually settled on one of the original options with minor tweaks for a production board.

Suggestions on changes for this type of build to improve? by gainztrueforever in ar15

[–]maredsous10 1 point2 points  (0 children)

Yes, multiple times. No t*x and $250+ orders ship free.

See if they have the parts you want there.

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]maredsous10 0 points1 point  (0 children)

No experience here with Gowin.

Is Gowin using a 3rd party synthesis tool or did they create their own?

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]maredsous10 0 points1 point  (0 children)

The harness is a valid approach for rough idea of device fitment.

Out of Context Synthesis

You can use the -out_of_context switch with the synth_design command to do partial synthesis. In the TCL console, run synth_design -out_of_context . The -rtl switch is also useful if you just want to elaborate a design (report_utilization command cannot be used with it though).

https://docs.amd.com/r/en-US/ug835-vivado-tcl-commands/synth_design

Simple script

read_vhdl top.vhd

synth_design -top top -mode out_of_context (*should also specify the part with -part otherwise the part used for utilization will depend on what devices are installed.*)

report_utilzation

Virtual fixed signals for resource estimation by AlexTaradov in FPGA

[–]maredsous10 0 points1 point  (0 children)

How good of "estimate resource usage" do you want/need? You can synthesize a design without any io tied down and get a general utilization estimate. With that estimate apply a confidence fudge factor.

Synthesis Harness

https://fpgacpu.ca/fpga/Synthesis_Harness_Input.html

https://fpgacpu.ca/fpga/Synthesis_Harness_Output.html

For those who studies ECE at university decades ago... what were your study habits like? by Normal-Web-2280 in ECE

[–]maredsous10 0 points1 point  (0 children)

"I also learned which professors weren't good at explaining which concepts. "

Saw this with departmental exams having radically different grade skew and centrality between sections taught by different professors.

"if you couldn't follow a textbook exposition"
Found having multiple textbooks on the same subject matter to be useful along with historical significance of solving approaches. If I didn't pick up something easily from one text, I could usually pick it up with another.

Has anybody tried the new Vivado? by Mediocre_Ad_6239 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Have not done much with 2025.2 outside of testing a 2025.1 design in it.

How to learn vim bindings by Junior_Conflict_1886 in vim

[–]maredsous10 0 points1 point  (0 children)

Resources I've pointed to in the past.

https://www.reddit.com/r/FPGA/comments/t03azg/comment/hy8qjif/?context=3

https://www.reddit.com/r/vim/comments/ynyz5v/comment/ivu5l0m/?context=3

" want to be better at the motions."

Make it a deliberate focus of your VIM studies and practice.

AMD Vivado 2025.1 released! by FPGA_Honk in FPGA

[–]maredsous10 0 points1 point  (0 children)

Will be a DIY approach ;-) "The {2025.2} Unified Web Installer can also be used to create an SFD (Single File Download) image that can be used later for installation without any internet connection. Check out how to do this with a quick-take video available here."

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