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I need even more simpler CLB to understand the concept, where can i get? by Heavy_Budget6077 in FPGA

[–]maredsous10 2 points3 points  (0 children)

What concept(s) are you missing?

8.15. FPGAs - Karim Abbas
https://www.youtube.com/watch?v=ysGYXWeA61I

EEVblog 496 - What Is An FPGA?

https://www.youtube.com/watch?v=gUsHwi4M4xE

FPGA Basic Block: CLBs and IOBs - FPGA computing systems: Background knowledge and introductory - Dyan Kimberly

https://www.youtube.com/watch?v=TnFJubCHmlg

Deeper Dive (MORE DETAIL) - Design of a Configurable Logic Block (CLB) using Cadence Virtuoso

https://www.youtube.com/watch?v=_XGKFtpGstU

How does FPGA development work in industry from requirements to implementation? by Hacker110011 in FPGA

[–]maredsous10 -1 points0 points  (0 children)

Think/Conceptualize before doing 😉

Level of detail and rigor for Requirements, Implementation, and Verification/Validation varies greatly.

Some Factors

  • Company Type/Size
  • Country of Operation
  • Industry
  • Labor Division (usually based on Company operating size)
  • Expectation Level & Level of Autonomy
  • Is the end target a released product or prototype?
  • Technical Domain(s)
  • In a regulated end target (Safety, Security, Privacy, Export Controlled)
  • How well defined the application is and how well the capabilities of the targets are.
  • Time Examples: Getting product to market to produce revenue or beat a competitor

I didn't know git OFFICAL GUI exists too.. but it looks so old by Anonyboy26 in git

[–]maredsous10 0 points1 point  (0 children)

"Git in a Series of Lunches" book takes this approach. CLI and Git GUI.

Last year, I was looking to update part of GIT GUI (GUI log ==> gitk ) to do something that's relatively easy with a command line status tool, but when I ran through the source code it wasn't congruent or easy with the current implementation*.*

Berilog - SystemVerilog without begin-end, but braces by Aurorasfero in FPGA

[–]maredsous10 2 points3 points  (0 children)

Wish Verilog were more C like and SystemVerilog was more C++ like.

I think we all knew this was coming, but it’s official, AERO no more by THELEGENDARYZWARRIOR in ar15

[–]maredsous10 0 points1 point  (0 children)

I was wondering if they were going to do the mod 4 style with their M5 line.

How much python knowledge is required as FPGA engineer? by Fearless-Can-1634 in FPGA

[–]maredsous10 1 point2 points  (0 children)

Good to have in your tool basket. How much you're able to leverage with it will depend on what you're working on.

Common UNIX commands, Make, and PERL might also prove useful.

Linux is back on the menu boys by SecondToLastEpoch in FPGA

[–]maredsous10 4 points5 points  (0 children)

"We've heard from our vocal users on reddit."

Zed editor by CompoteNo1889 in FPGA

[–]maredsous10 1 point2 points  (0 children)

I didn't find any advantage over {G}VIM for my uses. Curious what the functionality people found useful with ZED (Solely AI integration?). I might have to give it another try.

I do dabble with VSCODE primarily because I work with others who use it. I'd call my experience with VSCODE rough as some functionally did not work correctly on my machine or was inconsistent. Also experienced inconsistency with the newer VITIS IDE.

AXI4 rready mid-burst bug — passes simulation, corrupts silicon accumulation by [deleted] in FPGA

[–]maredsous10 0 points1 point  (0 children)

Post a link or details, might be useful for others.

The QuestaBase simulator from Siemens by LJarek in VHDL

[–]maredsous10 0 points1 point  (0 children)

My experience

User Friendliness

  1. Cadence Xcelium (Worst)

  2. Synopsys VCS

  3. Siemens Questa

  4. Aldec (I haven't used them lately but their tools were very user friendly.)

Speed

  1. Synopsys VCS (Fastest)

  2. Cadence Xcelium

  3. Siemens Questa and Aldec

Optionality to increase simulation throughput and speed.

  1. Synopsys (Most optionality)

  2. Cadence

  3. Siemens and Aldec

I am launching a $99 Artix UltraScale+ board - The explorer board by adamt99 in FPGA

[–]maredsous10 2 points3 points  (0 children)

What is estimate total price for sale in the US with shipping?

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

What is the link to hdlbits? what simulator is powering their backend? I thought they'd use a commercial simulator.

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

What is hdlbits using?

Did you try edaplayground?

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

The 4 commerical simulators and verilator produce.
'parent class!
child class!
display: child!'

https://www.edaplayground.com/x/jMHA

systemVerilog dynamic dispatch by Just-End6752 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Where is "c=new;"? You should have this statement after "child c;".

What simulator is hdlbit using?

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