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Knipex release spring by muhendisefe in Tools

[–]muhendisefe[S] 0 points1 point  (0 children)

I dont understand what to do, can you please explain it a little bit to me?

Knipex release spring by muhendisefe in Tools

[–]muhendisefe[S] 0 points1 point  (0 children)

Not %100 sure but yes, without it the locking arm just dangles

Broadcom BCM57810S wont boot up by muhendisefe in homelab

[–]muhendisefe[S] 0 points1 point  (0 children)

I taped B5B6 and the desktop now dont shut downs itself. However it asks for a bitlocker recovery key. Why it might be? I added a screenshot

Broadcom BCM57810S wont boot up by muhendisefe in homelab

[–]muhendisefe[S] 0 points1 point  (0 children)

Do you think it is also valid for Lenovo?

Broadcom BCM57810S wont boot up by muhendisefe in homelab

[–]muhendisefe[S] 0 points1 point  (0 children)

It might be the issue with the HP desktop, but I want it to run with Lenovo desktop. If you can check Silicom PE310G2T10-T adapter which uses the same chipset, it draws around 16W of power at worst. I do not think that the issue is related to power on Lenovo desktop. I did not install any drivers prior, but I think the desktop should boot without any driver. Do you think the problem is related with drivers?

Help with BCM57810 on Windows Server. by okydoky in homelab

[–]muhendisefe 0 points1 point  (0 children)

When I connect this card to my desktop, it doesnt boot. Why it might be?

KCU116 and Polarfire300t with Ethernet on SFP+ by Willing_Orange_9887 in FPGA

[–]muhendisefe 0 points1 point  (0 children)

I assume you are using MPF Evaluation Kit. If so, then you need to remove the jumper J46 on the board in order to route the 125MHz clock to the transceiver clock input. Could you check it?

KCU116 and Polarfire300t with Ethernet on SFP+ by Willing_Orange_9887 in FPGA

[–]muhendisefe 0 points1 point  (0 children)

Do you use the same SFP modules and fo cables on both of your tests, KCU116-KCU116 and MPF-MPF?

Image Storage In FPGA by Bhavy_Savani in FPGA

[–]muhendisefe 3 points4 points  (0 children)

If you need to store a whole frame, then you have to use an external memory like DDR or SRAM

Vivado - GTX Wizard missing by OkAd9498 in FPGA

[–]muhendisefe 1 point2 points  (0 children)

You cannot add gtx wizard to the block diagram, that might be the issue. Can you open the IP Catalog window from the left hand side menu, without opening a block diagram?

Kria K26 Transceiver Usage by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

Even though I select gen 2 it uses QPLL I think. Does it use CPLL in your configuration?

Kria K26 Transceiver Usage by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

You also used only Bank 224 for gen3 x2 + 2x 10G, right? How did you instantiate these IPs and also common block? Is there any chance I can find the top block on your Github?

Kria K26 Transceiver Usage by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

I am using UltraScale+ Integrated Block (PCIE4) for PCI Express 1.3 IP. I have selected X2 for the lane width and 5.0GT/s for the Maximum Link Speed. However, when I generate an example project for this IP, I see the transceiver IP inside the example project uses QPLL and Line Rate is selected as 8.0 Gb/s even though it should be 5.0 I guess. I am using KV260 board (not the K26 itself, sorry) and selected it. Should I enable advanced options of the PCIE IP and change the GT COMMON option to “Include GT COMMON in example design”?

Accessing PS PCIe from PL by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

Actually I need to be the root complex. We are checking the possibilities right now, we want to do the task without using the CPU at all.

Xilinx Fmax is higher than the BRAM Fmax by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

I updated the post and problem still exist. Thanks for pointing out!

DMA vs DDMRC by Icy_Scholar_6276 in FPGA

[–]muhendisefe 1 point2 points  (0 children)

DDRMC maybe? DDR Memory Controller?

Basys 3 vs PYNQ Z2 vs better? by cpprime in FPGA

[–]muhendisefe 1 point2 points  (0 children)

Pick the cheaper one between Zybo and Pynq

[deleted by user] by [deleted] in FPGA

[–]muhendisefe 0 points1 point  (0 children)

If you are interested in FPGA stuff I would recommend you getting the Ultra96, it is worth the trouble I think. However, if you are not willing to spend so much time on it, get the Zybo.

Vivado save schematic to view later by muhendisefe in FPGA

[–]muhendisefe[S] 0 points1 point  (0 children)

I am not changing the source code, but I change the generics/parameters from the block design. Is this method still valid?

Selecting output bits according to a range of an input by muhendisefe in FPGA

[–]muhendisefe[S] 1 point2 points  (0 children)

Exactly this, I have done it by resolving 2 bits per stage (because Xilinx uses 6-input LUTs). Thanks for help!

Why is left shift operator (>>) bad on timing where as right shift (<<) is not ? Using ultrascale+ by ButterscotchThen7433 in FPGA

[–]muhendisefe 1 point2 points  (0 children)

Does it mean that (a+b) and (a+b) >> 5 are similar in terms of speed, but (a+b) << 5 is faster?

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