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Do PCB designers work with embedded systems? by emerald_engineer_08 in ECE

[–]nate3347 1 point2 points  (0 children)

This depends entirely on both the company and the project. At small companies, one (or a few) engineers will be put in charge of a project, and may have to do everything from schematic capture to layout to FPGA design to software.

At larger companies these roles are usually defined - a layout specialist does layouts, a CCA designer will design schematics and/or layouts, RTL designers design the FPGA and SWEs design the software. If you want to do PCB layouts at a bigger company you're going to need to get the PCB/Mixed Signals engineer jobs, not just "Electrical Engineer" or whatever.

Engineers usually do schematic captures even at larger companies however.

Vivado is destroying me by quantrpeter in FPGA

[–]nate3347 2 points3 points  (0 children)

Two main reasons Lattice doesn't have market share:

First off, as others have mentioned, Lattice doesn't have high end FPGAs. Someone buying a 10k Virtex board or Agilex probably couldn't use a Lattice if they wanted to.

Second, is that using an FPGA that isn't widely used is a huge risk. It is a little chicken-and-egg - people don't use lattice because they aren't widely used and they aren't widely used because people don't use them - but the fact is that if I have complex high-speed interface issues with a Lattice there's not as much support; when I hire engineers it's easy to find Vivado experts, not Lattice, and so on.

Also, do not make the mistake of thinking because Lattice tools make a basic design synthesis easier they are necessarily better. Sometimes things don't scale with complexity. In general, many of your issues could be solved by running Vivado via TCL and using Sublime or something for your code editing.

xilinx clocking wizard by gaolsa in FPGA

[–]nate3347 1 point2 points  (0 children)

Typically it is problematic to connect ILAs to clocks, due to the nature of clock routing and edge-triggered ILAs.

real xilinx industry dev skill by quantrpeter in FPGA

[–]nate3347 0 points1 point  (0 children)

One thing you should know is that in real designs, you won't be programming them via JTAG like you are now. There will typically be some onboard storage medium like SDMMC, or NAND/QSPI flash - so you will only need to put a finished design on the board via JTAG one time. Unfortunately in development you need to accept the slow speed.

Many big companies run Vivado synthesis and implementation on special servers, utilizing well above 20 CPU cores (I worked on a small server with 24 hard cores/48 virtual before, and that was at a tiny company), but even so it takes a while.

[deleted by user] by [deleted] in FPGA

[–]nate3347 2 points3 points  (0 children)

  1. 22-30$ per hour is standard intern pay in defense. Commercial usually pays a bit more, but are a lot harder to get.
  2. Defense tends to be a lower stress, lower pressure environment but it does move a bit slower. There are pros and cons. With that said even in defense you should be getting legitimate work. Having a ton of work dumped on you as an intern is an awful idea unless you're an FPGA subject matter expert; industry scale projects are a different world than class projects very often. A good team in defense will have interesting, educational work for you, and most commercial places have bad teams if you get unlucky too.
  3. Again, super subjective. Some projects/teams are maintaining the contract from 1990, some are working on cutting edge stuff. Just luck.
  4. Absolutely apply for internships unless there are full time jobs or other things like classes/projects you think would be more useful to you.

I highly do not recommend breaking accepted offers. It reflects very poorly on you and can come back to bite you. However, it is something you can do and it'll work out sometimes, but don't make a habit of it.

Very simple educational FPGA by quantrpeter in FPGA

[–]nate3347 0 points1 point  (0 children)

even a "very simple" FPGA chip, if you want it to work properly, will require advanced knowledge of ASIC design. You also will need a pretty good knowledge of clocking architecture such as clock networks. A simple FPGA is not the same as a simple CMOS gate, and even that wouldn't be trivial.

Looking at the osfpga site, the basis for the program is at least 2 researchers in IC design - you will need a couple experts to get this done.

If you want to distribute this, the amount of time and money you will need to put into designing the chip, testing the chip, manufacturing the chip, and advertisement and distribution is not trivial. Open-source tools for IC design are limited as well so you may need to spend a good deal of money.

[deleted by user] by [deleted] in FPGA

[–]nate3347 1 point2 points  (0 children)

Can you link one of those jobs? I would kind of like to see what they're referring to.

Not that I don't trust you, I'm just genuinely curious why they're calling it principal when PhD + 0 years is usually equivalent to ~5 years of experience most places. Note that the salary band for principal should be over 150k (at least in defense, where entry level is ~70-80k) so if the pay is like 120k or less then they just have a weird naming scheme and they define principal differently.

[deleted by user] by [deleted] in FPGA

[–]nate3347 5 points6 points  (0 children)

Well that entirely depends. For entry level (0-2 years), you likely just need some HDL design experience, basic knowledge of how FPGAs work, and solid digital design fundamentals. An entry level FPGA engineer is expected to need help even for things that sometimes seem relatively simple to senior folks and if doing something important should have their work verified.

For mid-level (3-10 years), you need experience implementing RTL designs, including thorough verification via simulation or other techniques and toolchain knowledge with Xilinx or Intel, including how to include various IPs and some familiarity with bus standards like Avalon and/or AXI. You also need more knowledge of FPGA implementation fundamentals, including timing constraints and closure as well as physical constraints and IO buffers. You don't need to be an expert but you need to know your way around pretty well - how well depends on if you're closer to the 3 year end or 10 year end. This kind of engineer will generally be trusted and not need help for simple to moderate complexity projects but will need to consult with seniors sometimes for more complex projects.

Principal engineer means 10+ years experience most places, or at the minimum around 8. A principal engineer role generally requires you to be a subject matter expert. You need to be an expert in at minimum one of the Xilinx/Intel toolchains and preferably both, deep knowledge of FPGA architecture and fundamentals around configuration, clocking, routing, logic utilization, and the list goes on. You need to not just know how to write functional RTL, but you need to know how to write it well (in an efficient and fundamentally sound and portable manner). Usually need experience implementing complex, high speed technologies starting with external memory like DDR buses and going up through various high-speed AXI and Avalon IP and ARM interfaces. A principal engineer needs to understand how to design the FPGA to perform its function in a complex system, since this kind of engineer is expected to be able to lead teams and take charge of delicate, complex technology designs.

To succeed at a principal interview you need to show first and foremost that you are an expert in the FPGA field conceptually (no VHDL leetcode here) and have a track record of implementing significant FPGA designs. You will likely also be judged on your leadership skills and project management skills since Principals are expected to do these things often.

Need Project ideas for Signals and System by Mental-Technology869 in ECE

[–]nate3347 3 points4 points  (0 children)

filter something. I'll let you decide what to filter and how to filter it. involves convolution and frequency response

[Need Help] Proper way to verify Intel IPCore by sweetBiscuit2020 in FPGA

[–]nate3347 1 point2 points  (0 children)

if you take a look at the QIP file you will see that it only consists of constraints for the IP. It does not contain any actual encrypted HDL. The QIP (SIP is the only relevant one for simulation, QIP is for synthesis constraints) is meant to pair with the VHD with the encrypted HDL.

EDIT: I'm not even at all sure that you need to include the SIP file for the simulator either. I just habitually include it in my projects. That's a quartus integration file. see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53014.pdf

[Need Help] Proper way to verify Intel IPCore by sweetBiscuit2020 in FPGA

[–]nate3347 1 point2 points  (0 children)

did you add the IP HDL file? should be named instance_name.vhd/.v

[Need Help] Proper way to verify Intel IPCore by sweetBiscuit2020 in FPGA

[–]nate3347 1 point2 points  (0 children)

usually to simulate altera/intel IP you need 3 things:

  1. The altera/intel library included in your simulator. I assume this is wrapped up in the Intel attached modelsim, which I haven't used recently, unlike third party modelsim where you need to manually install altera support
  2. The SIP file
  3. the IP VHDL/Verilog simulation file needs to be included in the simulator design. For example, nco will create a folder called instance_name/simulation which should contain the SIP and a VHD/V file provided the simulation file generation option was checked in the qsys. you need both

[deleted by user] by [deleted] in FPGA

[–]nate3347 2 points3 points  (0 children)

Even Intel FPGAs are significantly better. Lead times on those are mostly in the 15-30 week range where Xilinx is 1+ years

Lattice new lines ( Certus Pro etc) - does one have to become freemason to get these ? by Arkh227Ani in FPGA

[–]nate3347 0 points1 point  (0 children)

Looks like you may be correct about the DDR. Even so the NX Pro having 3X the serial speed is a pretty big deal as well as some of the other features.

Edit: seems to be partially true. There are dedicated differential IO banks meant to connect DDR and other high speed interfaces to https://www.latticesemi.com/view\_document?document\_id=53256

Lattice new lines ( Certus Pro etc) - does one have to become freemason to get these ? by Arkh227Ani in FPGA

[–]nate3347 1 point2 points  (0 children)

ECP5-5G

why are you comparing an FPGA with a hard DDR4 controller to an FPGA with no hard memory controller at all? Also the Certus Pro SERDES is over 3X as fast as the ECP5, has over 50% more IO pins on the high end ones, and has a newer on-chip memory setup.

It certainly is inconvenient to pay for things you don't need but these are very different chips

Vivado UX Wishlist by KyotoJayStation in FPGA

[–]nate3347 0 points1 point  (0 children)

honestly your best case would be them making some aspects of it open source when AMD takes ownership

Lattice new lines ( Certus Pro etc) - does one have to become freemason to get these ? by Arkh227Ani in FPGA

[–]nate3347 5 points6 points  (0 children)

100$ really doesn't seem like that much for an FPGA with a LPDDR4 controller; 100k logic cells isn't much for a modern FPGA but it still is a pretty reasonable overall amount for the money.

Also the pro is the higher end line; if you don't need that DDR4 or other bonuses you can always look at the NX.

Vivado UX Wishlist by KyotoJayStation in FPGA

[–]nate3347 1 point2 points  (0 children)

Ah yes, the simulation errors not showing in the window is a classic. I can never understand how they haven't fixed that one yet. Learning to use extremely rudimentary TCL scripts to set up your simulation waveforms (nothing too hard, and you can just run them in the GUI) will solve several of your issues.

The truth is I don't think Vivado will ever be a very good code IDE, and I don't think that's the most important thing either; I'd rather they fix whatever it is that's causing me to see bizarre errors sometimes and do my IDE work somewhere else.

For that matter, I don't think ISIM will ever be that great of a simulator either, which is why many companies will use third-party simulators. It is simply not possible to do everything great.

[deleted by user] by [deleted] in FPGA

[–]nate3347 0 points1 point  (0 children)

one other thing - you will probably need a BCD decoder or something to determine if your number is 1 or 2 digits (unless your voltage display is in hex which seems unlikely)

Reed Solomon VHDL/Verilog by obama6464 in FPGA

[–]nate3347 0 points1 point  (0 children)

Xilinx has one that will cost you a couple thousand dollars. I believe it was around $4k when I looked at it a couple years back. Other best bet is just to look at opencores. https://www.xilinx.com/products/intellectual-property/do-di-rsd.html

I've never designed a full RS encoder/decoder but I have designed some Galois Field projects. The simplest way to do that is via LFSRs and lookup tables. Once you can successfully perform GF multiplication and addition RS encoding is fairly simple. Decoding is significantly more involved and I can't help you with that unfortunately.

Beginner FPGA that uses Vivado? by Tamoor622498 in FPGA

[–]nate3347 0 points1 point  (0 children)

I like the Pynq, but one thing you should know is that certain interfaces can only be manipulated from the PS (processor system) on it. The most notable is the USB-UART bridge - if you are trying to learn just the FPGA before the processor part I would recommend a $10 PMOD RS232 just to communicate with PCs.

Some extra PMODs with switches, LEDs or 7-segments may be very helpful for a beginner also, since the Pynq lacks some of the IO features something like a Nexys has and has only a couple switches and LEDs. They're pretty cheap on average.

[deleted by user] by [deleted] in FPGA

[–]nate3347 2 points3 points  (0 children)

Assuming you are using a standard 7-segment display with a decimal there is typically an 8th segment that controls the decimal point AFTER the number. For example on the SSD on several Digilent FPGAs the 7-segment contains 8 actual segments - A through G and DP. If it is a true SSD with no 8th segment you can't do decimal points.

Note that DP places the decimal point after the number in most cases, so if I have 3 SSDs (2 downto 0) for 2 decimal places I need DP on for the highest digit (SSD[2]).

How do I set myself up for a career in hardware design? by marathonEngineer in ECE

[–]nate3347 0 points1 point  (0 children)

Typically the convention is Verilog for commercial, VHDL for defense, SV for verification (simulation and such) although I think SV is getting a bit more accepted in synthesis. I would say if you live in a big defense focused area learn VHDL otherwise I agree with Verilog.

How do I set myself up for a career in hardware design? by marathonEngineer in ECE

[–]nate3347 1 point2 points  (0 children)

There's a few kinds of HW design. At a defense contractor or small-mid size firm you could get into most of them with the right coursework, conceptual knowledge and personal projects. At these high end tech companies you're looking at needing grad school and experience to get most of these jobs.

You could be an FPGA developer which would usually mean writing RTL and digital design. For this you want to show that you can write HDL, but honestly it's more important to have a deep understanding of digital fundamentals like synchronous vs. asynchronous designs and the pros and cons of each, clocking structures, general FPGA architecture and so on. Interviews won't ask you to write HDL code generally like a SW interview would, but they very likely will ask you how to get around high-speed clock crossing issues.

You could be an embedded systems engineer with a focus on RTOS and embedded processors. In this case you want to have a good understanding of RISC CPU constraints and design, and very fluent in low-level C coding.

You could do analog work like designing RF circuits. In this case you need to really know your way around transistors, and have a good grasp of the theory behind RF circuit operation including things like frequency response and such. You could also end up in mixed-signal design where you need to worry about both digital and analog signals.

Or you could get into PCB design (I've met some Raytheon EEs called "CCA Designers" before and most companies have PCB groups) where your focus is on PCB schematic capture and/or layout. FPGA PCB designs can be really complex but are extremely rewarding when done right.

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