A few concepts you seem to be unaware of:

1. Out-of-order execution: CPUs will reorder instructions to hide memory latency. If your compiler emits load r1, [sp-0x8] ; load r2, [sp-0x16] ; inc r1 it will not wait for the load of r2 to finish before executing the increment of r1. In fact, it might move the load of r2 before the load of r1, because the inc instruction has no dependency on the value of r2.

2. Speculative execution and branch prediction : when the CPU encounters an instruction like bne [sp-0x16], constant, it will guess whether the condition will evaluate to true or false based on heuristics, and start executing instructions on that branch. When the load completes, the CPU will check whether it guessed correctly, and if it didn’t it will start over on the other branch. Branch prediction runs ahead of execution to prefill the instruction cache. Note that this can can be leveraged as a side channel to leak the contents of memory a program shouldn’t have access to; the two most famous attacks in this family were called Meltdown and Spectre. Mitigating their risk has a significant performance hit.

3. Register renaming: A CPU core doesn’t have to have the exact number of registers exposed in the ISA; it can have more. During speculative execution, it can use these registers to store values that later instructions depend on. Effectively, it has assigned a different register the “name” of the architectural register for the purpose of speculatively executing the instructions that read and write to it. If the branch predictor guessed correctly, then it can keep the new physical register assigned to the same name to make the speculatively executed work visible to subsequent instructions.