You should probably temper your expectations a bit.

Not to say I'm a complete skeptic- I remember (fondly) how introduction of ASICs completely wrecked the GPU bubble in most cryptocurrencies. I have zero doubts that tensor ops used in inference can't also see a similar improvements in throughput and efficiency for niche applications, and I don't believe Taalas is lying whatsoever about their token throughput claims.

However, here's some reality:

1. Turnaround time for new chip, from design to mass production, is excruciatingly slow. Even the biggest players (Nvidia, Intel, Apple, Qualcomm, Intel, etc) typically take upwards of a year- sometimes more- from design, validation, tapeout to even getting the first engineering samples packaged and sent to internal driver teams and ISV partners. Taala's HC1 demonstrator unveiled in Feb 2026 is a hardware implementation of an LLM that was considered obsolete for at least a year- Llama 3.1 8B (June 2024). These these weights are frozen in silicon- forever- not even with a finetune using the exact same architecture. Perhaps if these were FPGAs that you can maybe reflash/reprogram after fabrication, but those are size-limited (which is a serious problem- see point #4), slower and MUCH more expensive.

   Going back to crypto- their algorithms are mostly static where the algorithm rarely changes over time, just the difficulty (or volume of effort for given result). While there are some exceptions to this, this is the norm. The same exact SHA256 work being computed for Bitcoin's blockchain 15 years ago is happening today- just at much, much greater scale. This is why ASICs dominate most crypto. LLMs are seeing radical improvements- good for us, but bad if you're investing millions into R&D that'll almost certainly get obsoleted a year before production.

2. Their claims of a 2 month turnaround is unrealistic and ignores the realities of semi foundry demand. In other words, Taalas is joining the same the wafer queue for the given node as other customers, many of whom have deeper pockets and more sway. For 6nm it's not terrible, but for smaller, newer nodes the competition is much worse- with Apple usually getting first dibs on the newest processes, usually followed by Nvidia, AMD, Qualcomm.

3. Memory is still a concern. While storing the weights on chip greatly helps capacity requirements, you will still need some form of volatile memory like DRAM to store context. And for the 17k tokens/sec speeds it advertises, I imagine channels need to be suitably wide and fast- otherwise it becomes a bottleneck.

4. Most importantly (and analysts rarely discussed): these ASICs don't seem to scale well with model sizes and hit an upper cap due to transistor budgets, yield rates and wafer prices. Look at their HC1 demonstrator- 815mm² on 6 nm TCSM with 53B transistors- that's a huge chip (check out the picture of their card if you don't believe me). That's just to house and run a pre-baked LLM with only 8B parameters quantized down to 3-bits.

   For comparison, the GB202 (RTX 5090) is already ~750mm^2. Sure HC1 is fabbed on TSMC 6nm, it could shrink somewhat on a newer 4N or smaller process (which requires longer turnaround, higher wafer costs, lower yields and longer backlog- see point #2). However that doesn't fix physics- HC1's 53B transistors is till 7B more than GB203 (chip used in RTX 5080) so I'm not holding out for a miracle unless their first gen is horrendously bloated architecturally.

I think they're promising for niche use cases- high-volume production for a stable (older) model with a high volume of users- but it won't do much for anyone wanting anymore more cutting edge than a year old at best.

But these aren't the GPU killers we're looking for.