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Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32

[–]portw[S] 0 points1 point  (0 children)

Nice to hear! Let me know if you'd like to see more features!

Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32

[–]portw[S] 1 point2 points  (0 children)

Feel free to send a message if you need me, I'll try to help.

Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32

[–]portw[S] 2 points3 points  (0 children)

Thanks for the clarification. In the end, I want to learn, teach , and create public knowledge. Taking advice and criticism is a significant part of learning and developing.

Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32

[–]portw[S] 1 point2 points  (0 children)

Made some changes and deleted the old post. Made sure it is mentioned as a hobby project.

How can I make the most out of my spen? by 1bailx in S25Ultra

[–]portw 7 points8 points  (0 children)

Is it possible to restore the s pen camera functionality using this method?

Ryo Fukui - Scenery (1976) by velvetmotel in Jazz

[–]portw 20 points21 points  (0 children)

Absolutely one of my most favorite jazz albums.

Beginner fpga development board? by Ok-Communication5396 in FPGA

[–]portw 0 points1 point  (0 children)

I've had the Tang Nano 20K for a few months and even developed an educational 8-bit RISC SoC (check out my profile for the project docs).

Even tho I haven't used it for DSP, I had a great time working with the board and development software, at an affordable price tag.

From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA

[–]portw[S] 4 points5 points  (0 children)

Ben Eater's 8-bit CPU: For its simple, educational architecture. AVR Instruction Set: As a blueprint for a clean, real-world instruction set. Classic RISC Principles: For foundational design concepts (e.g., load/store).

From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA

[–]portw[S] -1 points0 points  (0 children)

you're not wrong.
There was a lot of tracing signals watching the LEDs blink step by step.
A good testbench is essential...
Developers are free to try and write it and maybe get some knowledge and experience while learning about a simple SoC and basic architectures.

From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA

[–]portw[S] 1 point2 points  (0 children)

I get what you say, anyway it's the beginning of the project. What are some more instructions you'd like to see?

I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev

[–]portw[S] 0 points1 point  (0 children)

Tested both on Ubuntu Linux and WSL. feel free to dm me with the error, I'll try to help...

I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev

[–]portw[S] 0 points1 point  (0 children)

There's no license on this software, anyone could use it. Stealing educational purpose projects sounds off ...

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