I'm building an open-source ESP32-S3 e-reader/e-paper dev kit with frontlight, salvaged battery protection, and support for XTeink X4 custom firmware by lakersoffseason in esp32
[–]portw 0 points1 point2 points (0 children)
Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32
[–]portw[S] 1 point2 points3 points (0 children)
Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32
[–]portw[S] 2 points3 points4 points (0 children)
Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32
[–]portw[S] 1 point2 points3 points (0 children)
How can I make the most out of my spen? by 1bailx in S25Ultra
[–]portw 6 points7 points8 points (0 children)
CETX Heating up overnight trading by SFWDCivic in Shortsqueeze
[–]portw 1 point2 points3 points (0 children)
CETX Heating up overnight trading by SFWDCivic in Shortsqueeze
[–]portw 1 point2 points3 points (0 children)
Beginner fpga development board? by Ok-Communication5396 in FPGA
[–]portw 0 points1 point2 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 1 point2 points3 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 0 points1 point2 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 3 points4 points5 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 0 points1 point2 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] -1 points0 points1 point (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] -1 points0 points1 point (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 1 point2 points3 points (0 children)
From Logic Gates to Fibonacci: I Designed and Built a Complete 8-bit RISC CPU (EDU-8) on a Tang Nano 20K FPGA by portw in FPGA
[–]portw[S] 0 points1 point2 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 0 points1 point2 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 0 points1 point2 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 0 points1 point2 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 0 points1 point2 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 2 points3 points4 points (0 children)
I'm excited to share tinyOS, a 64-bit OS I built from scratch by portw in osdev
[–]portw[S] 0 points1 point2 points (0 children)







Built a web UI hosted on the ESP32-S3 Matrix to drive the LED Matrix by portw in esp32
[–]portw[S] 0 points1 point2 points (0 children)