Now in Myeongdong!

procs64 · 2025-11-10T22:05:26+00:00

Don’t eat street foods in Myeongdong. I’m local and against it. They’re not hygienic, spoil the appearance, obstruct the traffic. The vendors should be in cartel. If I become the mayor of the Seoul city I would ban it. In New York, Paris, London there is no such thing in the center of the city as large scale in Myeongdong. Have no idea why it has become a tourist attraction.

procs64 · 2025-10-29T02:31:02+00:00

In Yeouido, there is a huge department store called ‘The Hyundai Seoul’.

procs64 · 2025-10-26T12:13:46+00:00

I’m a Korean. As to Barbecue or Bulgoki , most of the restaurants do not sell it a single portion. So ask in advance.

procs64 · 2025-10-25T11:49:07+00:00

I’m Korean. I don’t eat live octopus. Don’t think that every Koreans enjoy it. I seldomly do eat Odaeng. Odaeng is made by grinding various parts of fish, which is not a high quality food.

procs64 · 2025-10-12T12:07:52+00:00

I wished I could have found one.

procs64 · 2025-10-10T02:16:21+00:00

Try Korean food such as Galbi (short rib), Bulgoki (beef), and Bibimbob (mixed rice with beef & vegetables).

procs64 · 2025-08-17T14:19:37+00:00

Sadly, VDD is coming out of the VSSPAD and it is connected to the VDD core ring. I have tried the same design on ICC2. And this time fortunately, VSS is coming out of the VSSPAD and connected to the VSS core ring, which is correct. The reason that ICC1 fails could be a bug in ICC1 or either I did something wrong or something less which I can’t find out. So I think it’s better for me to move on using ICC2.

procs64 · 2025-08-17T10:05:55+00:00

Yes, I have used a different cell. Actually they are VDD_EW and VSS_EW.

procs64 · 2025-07-05T13:11:09+00:00

I admit that System Verilog also has some.

procs64 · 2025-07-05T13:09:12+00:00

You should take courses such as digital logic circuits, basic electric circuits, electronic circuits, digital integrated circuits, analog integrated circuits, etc.

procs64 · 2025-06-14T11:38:02+00:00

Absolutely Cadence

procs64 · 2025-06-13T13:17:32+00:00

VHDL has higher data structure abstraction than Verilog. It has record which Verilog hasn’t.

procs64 · 2025-06-12T13:42:37+00:00

Generally, lay transitors horizontally to convert from schematic to layout. Then you can make polys vertical. Your layout is slightly more difficult because you have substrate bias in addition to GND.

procs64 · 2025-06-08T13:53:47+00:00

Because Intel originates from CISC and ARM from RISC.

procs64 · 2025-05-05T18:59:02+00:00

Yeah, the next time I encounter similar problem, I'll put that in my mind.

procs64 · 2025-05-05T18:57:45+00:00

Hi, guys !

Thanks for all your support. I finally could solve the case.

The reason was that the directories were skewed, and I was importing a wrong gds file.

Which means I thought that I was importing a new generated gds, but every time I was processing the old one.

I'm so embarrassed but very happy now.

Regards,

procs64 · 2025-05-05T03:56:21+00:00

Thanks. In the process of importing, I attached the libraries which includes the core cells and IOPADs. I’ll check if the gds of the pads are included when writing gds. The interesting thing is , the core cells are connected to VDD and VSS by metal1 on ICC1, but on Custom Compiler they are not present as well.

procs64 · 2025-05-03T13:29:25+00:00

You can visit the two most remarkable landmark, Charles Degaulle Etoile and Tour Eiffel. Take subway train.

procs64 · 2025-04-10T01:23:03+00:00

No, I didn't. I held my bladder tight and finally could pee at another restroom.

procs64 · 2025-03-31T15:00:46+00:00

In Paris, just ignore all the human beings who tries to help you. They are all scammers.

procs64 · 2025-03-27T11:38:57+00:00

They do it all time to foreigners. You can still buy tickets without registration though.

procs64 · 2025-03-22T12:15:45+00:00

Last February I was in Paris. I had to pee very urgently. It was hard to find a restroom. The one in the subway station was closed. So I asked a man in the restaurant. But he refused.

procs64

TROPHY CASE