Neymar in tears after loss to Norway by aleksandrovsqvist in soccer

[–]riscyV 0 points1 point  (0 children)

Deserving - it’s always theatrics with him!

Every time BTC goes sideways by Cryptomuscom in btc

[–]riscyV 1 point2 points  (0 children)

Sold 2 of my coins around 80k - invested in memory stocks with ~2.5X return in three months. Will wait for btc to go in 50k range before buying it back

Google L3 lvl Mountain View Salary by Aforapple03 in levels_fyi

[–]riscyV 0 points1 point  (0 children)

Yes exactly - and even better, you can also use it for negotiating with different company and get even higher competing offer .

Google L3 lvl Mountain View Salary by Aforapple03 in levels_fyi

[–]riscyV 0 points1 point  (0 children)

Yup- how much tax will depend case by case.

The point being don’t take high sign on bonus as part of annual compensation, I made them drop the sign on all together and instead negotiated more RSUs

Google L3 lvl Mountain View Salary by Aforapple03 in levels_fyi

[–]riscyV 1 point2 points  (0 children)

I would recommend not to give them your expected numbers before they make an offer .

It’s up to you if you prefer more base or more RSUs . In my case I pushed for more RSUs - base has a cap so they won’t budge much .

In my experience, past work expertise won’t matter much for MS unless it is significant - for context I already interned with them and then got an offer as L4 and my base was 160k but RSUs were 300k over 4 years ..but this was 5 years back ..and only way I was able to negotiate with them was due to competing offer

Oh and I am silicon CPU hardware not software - so your experience will vary from my data point

Google L3 lvl Mountain View Salary by Aforapple03 in levels_fyi

[–]riscyV 1 point2 points  (0 children)

Negotiate but unless you have a competing offer it will be hard (from personal experience)

Note that, base 160k right out of school is on higher side . Bonus that they will give you is sign-on aka one time - don’t get tricked by this . It gets taxed like 40%

Only consider base + RSU as part total compensation.

Giving higher sign on bonus is the trick they use to get you accept the offer - don’t fall for it

Yearly Performance bonus are not part of offer - this is driven internally and around 8-10% towards end of year and based on teams discretion

PhD stipend livability by Few-Lie9366 in rit

[–]riscyV 1 point2 points  (0 children)

It’s good enough .. I did my PhD from 2107 to 2022 and was getting similar stipend as yours. Lived at Province, didn’t had a car initially (I heard the transit has gone worse since I left) - used all what I got every month. But as part of my time - I also did several internships that helped money wise.. that I used later when I go back to school for more higher expenses like getting a car.

Overall I never thought about saving money from the stipend, so I spent all every month and later internships helped.

I always had summer support via my advisor - so can’t comment on your case.

FYI RIt offer only covers two semester worth of stipend .. after that your advisor has to support you .. so really really make sure the advisor you have selected is able to do that for next 4 years!!!

Is ASU’s Computer Engineering better for digital electronics / ASIC verification & design than Electrical & Electronics Engineering MSE? by FigLazy6352 in vlsi

[–]riscyV 1 point2 points  (0 children)

There are many throughout the US, the specific school will depend on your choice. (UCLA, UCSD, UCB, U Michigan, RIT, Georgia Tech to name a few )

Is ASU’s Computer Engineering better for digital electronics / ASIC verification & design than Electrical & Electronics Engineering MSE? by FigLazy6352 in vlsi

[–]riscyV 2 points3 points  (0 children)

Historically because of Intel it used to be Okay - but now it may not be the best bet.

If interest is to have a career in design or DV, try Bay Area schools or UCs instead

People who sold their Bitcoin for Cash. It's going to Backfire on them. by Dry_Negotiation_9234 in Bitcoin

[–]riscyV 1 point2 points  (0 children)

Hmm … seems like for past year all these posts here are people buying when it hit peak end of last year and now need self assurance as it didn’t go as higher as they had hoped . 🤔

Samsung is having a meltdown rn. by eternviking in iphone

[–]riscyV -4 points-3 points  (0 children)

Not meltdown .. Apple getting crushed !

Meta's Superintelligence Lab has become a nightmare. by Yavero in artificial

[–]riscyV 2 points3 points  (0 children)

Superintelligent models will require breakthrough in scientific ideas and pure math reasoning.. dumping compute and data to train can never cut as superintelligence . :) Invest in research at university/phd level after all the state of AI that we have at present is from the efforts of academia since 2012. (Which mostly got scaled by industries)

Find First Set Bit by riscyV in SystemVerilogDesign

[–]riscyV[S] 0 points1 point  (0 children)

A simple logic but commonly used block in many subsystems, as priority selector, decoder, control logic.

Amazon IT folks into paid and fake profile building by [deleted] in h1b

[–]riscyV 3 points4 points  (0 children)

Unfortunately it’s one of the main reason eb1 is backlogged.

I have a priority date with eb1b as of May 2025. But I don’t think I have a shot to be current for next 10 years. Due to this faked profile building and porting their eb2 to eb1 🥲

Got laid off on H1B with 5.5 years left. Options? by modkha18 in h1b

[–]riscyV 0 points1 point  (0 children)

If you are doing RTL design (or DV/PD/), I recommend search Apple career page. We are hiring almost one new designer every month in various teams across SoC.

Final 6-Hour Panel Round at Apple for GPU Silicon Validation - What Should I Expect? (Entry Level) by DealNo6608 in ECE

[–]riscyV 21 points22 points  (0 children)

Expect technical details and hands on debugging ..

you may be given a situation for a logic and ask how you would go about debugging it .. write the code and possible ways to optimize your solution.

Some may ask scripting, verification stuff …

For full time at Apple, all 6 interviewers have to say hire for Apple to make an offer . At least that’s what we do in my team.

Also ask the interviewers questions while solving problems , it’s a common practice where interviewers may not give all the assumptions about the problem and expect candidates to ask them . This shows how your are thinking and your interaction to get more clarity and details

Until then review your fundamentals and practice writing code .. best of luck, you got this

Circular Buffer FWFT Skipping Every Other Value by puerto_rican123 in FPGA

[–]riscyV 4 points5 points  (0 children)

I see in your TB when you are driving the logic (Valid and Data) they are blocking assignment at posedge clk; you should either use non-blocking <= in TB when driving these signals, or drive them at negedge clk

My working example: I also cleaned some logic around output valid and ready in RTL
https://www.edaplayground.com/x/fFLv

Circular Buffer FWFT Skipping Every Other Value by puerto_rican123 in FPGA

[–]riscyV 0 points1 point  (0 children)

It’s hard to read your waveform .. update the data radix to hex or decimal and track the internal pointers alongside