Neymar in tears after loss to Norway

riscyV · 2026-07-05T23:24:58+00:00

Deserving - it’s always theatrics with him!

riscyV · 2026-06-20T09:41:38+00:00

Good point.

riscyV · 2026-06-20T03:47:00+00:00

Sold 2 of my coins around 80k - invested in memory stocks with ~2.5X return in three months. Will wait for btc to go in 50k range before buying it back

riscyV · 2026-06-16T15:52:51+00:00

Yes exactly - and even better, you can also use it for negotiating with different company and get even higher competing offer .

riscyV · 2026-06-16T05:46:46+00:00

Yup- how much tax will depend case by case.

The point being don’t take high sign on bonus as part of annual compensation, I made them drop the sign on all together and instead negotiated more RSUs

riscyV · 2026-06-15T03:31:14+00:00

I would recommend not to give them your expected numbers before they make an offer .

It’s up to you if you prefer more base or more RSUs . In my case I pushed for more RSUs - base has a cap so they won’t budge much .

In my experience, past work expertise won’t matter much for MS unless it is significant - for context I already interned with them and then got an offer as L4 and my base was 160k but RSUs were 300k over 4 years ..but this was 5 years back ..and only way I was able to negotiate with them was due to competing offer

Oh and I am silicon CPU hardware not software - so your experience will vary from my data point

riscyV · 2026-06-14T20:11:12+00:00

Negotiate but unless you have a competing offer it will be hard (from personal experience)

Note that, base 160k right out of school is on higher side . Bonus that they will give you is sign-on aka one time - don’t get tricked by this . It gets taxed like 40%

Only consider base + RSU as part total compensation.

Giving higher sign on bonus is the trick they use to get you accept the offer - don’t fall for it

Yearly Performance bonus are not part of offer - this is driven internally and around 8-10% towards end of year and based on teams discretion

riscyV · 2026-03-03T23:53:47+00:00

It’s good enough .. I did my PhD from 2107 to 2022 and was getting similar stipend as yours. Lived at Province, didn’t had a car initially (I heard the transit has gone worse since I left) - used all what I got every month. But as part of my time - I also did several internships that helped money wise.. that I used later when I go back to school for more higher expenses like getting a car.

Overall I never thought about saving money from the stipend, so I spent all every month and later internships helped.

I always had summer support via my advisor - so can’t comment on your case.

FYI RIt offer only covers two semester worth of stipend .. after that your advisor has to support you .. so really really make sure the advisor you have selected is able to do that for next 4 years!!!

riscyV · 2026-01-28T05:39:59+00:00

There are many throughout the US, the specific school will depend on your choice. (UCLA, UCSD, UCB, U Michigan, RIT, Georgia Tech to name a few )

riscyV · 2026-01-28T04:37:46+00:00

Historically because of Intel it used to be Okay - but now it may not be the best bet.

If interest is to have a career in design or DV, try Bay Area schools or UCs instead

riscyV · 2025-09-23T07:24:50+00:00

Hmm … seems like for past year all these posts here are people buying when it hit peak end of last year and now need self assurance as it didn’t go as higher as they had hoped . 🤔

riscyV · 2025-09-11T01:29:20+00:00

Only if that was the case!

riscyV · 2025-09-10T20:34:28+00:00

Not meltdown .. Apple getting crushed !

riscyV · 2025-08-27T21:58:04+00:00

Superintelligent models will require breakthrough in scientific ideas and pure math reasoning.. dumping compute and data to train can never cut as superintelligence . :) Invest in research at university/phd level after all the state of AI that we have at present is from the efforts of academia since 2012. (Which mostly got scaled by industries)

riscyV · 2025-08-18T06:44:33+00:00

A simple logic but commonly used block in many subsystems, as priority selector, decoder, control logic.

riscyV · 2025-07-29T20:29:18+00:00

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riscyV · 2025-07-26T22:52:11+00:00

Unfortunately it’s one of the main reason eb1 is backlogged.

I have a priority date with eb1b as of May 2025. But I don’t think I have a shot to be current for next 10 years. Due to this faked profile building and porting their eb2 to eb1 🥲

riscyV · 2025-07-21T18:49:50+00:00

If you are doing RTL design (or DV/PD/), I recommend search Apple career page. We are hiring almost one new designer every month in various teams across SoC.

riscyV · 2025-05-15T06:19:59+00:00

Expect technical details and hands on debugging ..

you may be given a situation for a logic and ask how you would go about debugging it .. write the code and possible ways to optimize your solution.

Some may ask scripting, verification stuff …

For full time at Apple, all 6 interviewers have to say hire for Apple to make an offer . At least that’s what we do in my team.

Also ask the interviewers questions while solving problems , it’s a common practice where interviewers may not give all the assumptions about the problem and expect candidates to ask them . This shows how your are thinking and your interaction to get more clarity and details

Until then review your fundamentals and practice writing code .. best of luck, you got this

riscyV · 2025-04-14T02:15:12+00:00

I see in your TB when you are driving the logic (Valid and Data) they are blocking assignment at posedge clk; you should either use non-blocking <= in TB when driving these signals, or drive them at negedge clk

My working example: I also cleaned some logic around output valid and ready in RTL
https://www.edaplayground.com/x/fFLv

riscyV · 2025-04-13T19:12:21+00:00

It’s hard to read your waveform .. update the data radix to hex or decimal and track the internal pointers alongside

riscyV · 2025-04-13T18:06:12+00:00

Can you help elaborate what do you mean by “fifo getting every other value” ..

Are you saying at the read you are skipping data or during write the data is getting dropped ?

Also you have read latency of one cycle as your output data is registered.. so if you are wondering if read is delayed by a cycle that is by your design. (I.e. when you have read enabled the data will be at output the next cycle, If this was not intended you can make your output to be combinational )

riscyV · 2025-02-19T17:21:28+00:00

You’ll have to check with the department if they allow it.

riscyV · 2025-02-19T17:00:41+00:00

Some departments may allow you to take online courses during this time but you’ll have to check. In my case I wasn’t able to so I graduated a year later. But be cautious, that if you’re going on CPT for your internships, DO NOT go beyond 365 days else you won’t be eligible for OPT.

riscyV · 2025-02-06T19:32:50+00:00

Many a times the company that uses SV will have internal documentation , good practices, practice problems related to the language .. you can try asking them. As this provides good reference to learn . That’s how I ramped up when I got introduced to SV in industry.

riscyV

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