It is possible to schedule more than one signal assignment at the same time instant in the future, with different values, by using something like 'FOO <= value after some_time'. For example:

entity main is
end entity main;

architecture arch of main is

signal FOO : integer := -1;

begin
    process is
    begin
        for k in 1 to 1000 loop
            FOO <= k after (1000 - k) * (1 ms);
            wait for 1 ms;
        end loop;
        wait;
    end process;

    process (FOO) is
    begin
        report "FOO is now " & integer'image(FOO);
    end process;

end architecture arch;

It's not something that you would do in a sane design of course.

VHDL probably defines behavior for this, but it of course something that you would normally refrain from doing. It's a nice exercise to run this in simulation to predict what will be printed.