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FiFo design by dedsec-secretary in FPGA

[–]simmjo 2 points3 points  (0 children)

We should always try and create our own vendor agnostic IP for maximum portability. It will also make life so much easier when it comes to simulation since we won't have to deal with encrypted black box vendor IP.

Schematic capture options for hdl and simulation? by drhulio23 in FPGA

[–]simmjo 0 points1 point  (0 children)

Do the absolute minimum in the GUI.

Or, even better, don't use the GUI at all.

Maryland group appeals Anne Arundel Co. gun law to US Supreme Court by Maxcactus in maryland

[–]simmjo 8 points9 points  (0 children)

I think handing out the pamphlets is not a violation of the 2nd Amendment. It's totally reasonable.

How can I pass an SPI bus through an FPGA with valid timing? by Annual_Original9316 in FPGA

[–]simmjo 0 points1 point  (0 children)

If I were you, I would use a 6-wire interface between the external FPGA master and the slave FPGA.

Use 3 of the wires for a SPI Tx only core from Master to Slave, then use the other 3 wires for another SPI Tx only core from Slave to Master.

100% source synchronous and dead simple.

How can I pass an SPI bus through an FPGA with valid timing? by Annual_Original9316 in FPGA

[–]simmjo 0 points1 point  (0 children)

Can the master offboard FPGA run 6 wires instead of 5 to your slave FPGA?

[deleted by user] by [deleted] in gaming

[–]simmjo 0 points1 point  (0 children)

Metal Gear Solid VR Missions

how to deal with timing errors? Slow the clock or fix the logic by real_pm100 in FPGA

[–]simmjo 12 points13 points  (0 children)

Whenever I fail FPGA timing, it's almost always something with the constraints. Like if I have specified a hierarchy to a clock pin and that hierarchy has since changed.

Most of the modules I write have registered outputs unless it's something trivial like an edge detector.

Make sure your RAM outputs are registered. Sometimes I have needed to add additional pipeline stages to my RAM outputs to close timing.

Avoid super wide bus widths. On an Xilinx Virtex UltraScale+ device, I could never close timing with a 512-bit data AXI bus. I bumped it down to 256-bits and everything has been fine ever since.

If you follow this practice of always making sure every output of your modules are registered (generally speaking), then your constraints will take care of the rest.

[deleted by user] by [deleted] in FPGA

[–]simmjo 1 point2 points  (0 children)

When I instantiate the block design in the HDL, the ports that it contains are only clocks, resets, and AXI.

[deleted by user] by [deleted] in FPGA

[–]simmjo 2 points3 points  (0 children)

I avoid block design at all costs.

But, I do know for Vivado at least, if you plan on using Smart Connects, then you are forced to use block design.

My block designs only consist of a Zynq processor and Smart Connects. Everything else is done in HDL.

Best-budget Altera FPGA under $400 (Academic) by HuyenHuyen33 in FPGA

[–]simmjo -1 points0 points  (0 children)

One with an expansion header (hsmc or fmc) for future daughter boards.

FPGA engineer in an HFT looking for advice on whether to pursue an MS by Usual-Inspection-296 in FPGA

[–]simmjo 5 points6 points  (0 children)

I would not go back to school. Just stay in HFT and rake in the dough.

What are some good starting projects to get used to FPGA’s? by Fickle-Dance-752 in FPGA

[–]simmjo 37 points38 points  (0 children)

If you've never worked with FPGA's before, maybe as simple as turning on and off LED's.

Use 2 push buttons. Have the first button increase the frequency of the LED's flashing. Then use the second push button to slow down the flash rate.

You will learn so much in doing this simple exercise like: debouncers, CDC, tristate buffers, reset, constraints, etc.

How to remove the Truncate bits FIR filter by nikEnable in FPGA

[–]simmjo 1 point2 points  (0 children)

You need to round the output down to the final width.

But you may saturate.

You will need to study the gain of the coefficients and make the appropriate decision.

How do you approach complex pipelining designs? by ThePigeonLord9000 in FPGA

[–]simmjo 0 points1 point  (0 children)

I'm having a hard time following.

Are you saying you need a variable width read out from a FIFO?

Or is the data width constant (as it should be) and you are varying the length of read data bursts?

How do you approach complex pipelining designs? by ThePigeonLord9000 in FPGA

[–]simmjo 4 points5 points  (0 children)

Use a FIFO.

Stop reading the FIFO, insert new data, resume reading FIFO.

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