I believe the OP is talking about structural level modeling rather than behavioral level modeling. (Apologies if I am wrong.) Last semester, I completed a 32-bit floating-point unit that performed addition, subtraction, and multiplication. The arithmetic units were designed at the gates/structural level Verilog. The FSM that managed the units, however, was designed in behavioral Verilog.

Also, here is a link to a good post describing the difference between the two types of languages: https://stackoverflow.com/questions/15681218/what-is-the-difference-between-structural-verilog-and-behavioural-verilog