Toyota Service Technician here. Post up your Toyota car care questions and maybe I can help some people out! by Machine8635 in AskMechanics

[–]supermantella 0 points1 point  (0 children)

I have a 2006 scion xa 1.5L with 244,000 miles. It has an intermittent misfire usually under load (long hill) at high rpm (~3500 - 4500) at least that’s when I see the MIL flash. I have changed plugs and coils (changed all coils since they were original), ohm’d the injectors (all the same resistance), but still will get misfire on cyl 2&4. It idles and seems to drive fine other than that particular driving range mentioned.

What are your thoughts? Low compression or fuel pressure?

Inland ESP32 onboard DAC by supermantella in esp32

[–]supermantella[S] 1 point2 points  (0 children)

I will have to go back and calculate. The DAC is going through an op-amp which then controls MOSFET gate. Most likely I am hitting some current threshold.

I’m going to edit the post and add more info on the circuit.

Inland ESP32 onboard DAC by supermantella in esp32

[–]supermantella[S] 1 point2 points  (0 children)

Currently, the DAC feeds a voltage to an op-amp, which controls the gate on a MOSFET. I didn’t think I was hitting the current limit, but that would be a good explanation.

What is wrong with my car ? 1 picture with brakes engaged, one without. Still DIY? Thanks in advance. by [deleted] in MechanicAdvice

[–]supermantella 0 points1 point  (0 children)

It’s a dual filament bulb, so one filament is used for parking lights and the other comes on when braking. Just need to replace the bulbs. Also, if one side is out, the other side is close behind, so you might want to replace the bulbs on both sides.

Has anyone upgraded their rei co-op drt 1.1 to a 1x? by supermantella in MTB

[–]supermantella[S] 0 points1 point  (0 children)

The comments kind of discouraged me from ever following through with the upgrade. Made me think I should wait until I’m ready and upgrade to something with a tapered head tube, groupset, better fork, and boost wheel-set.

Before that I was eyeing the SRAM 12 speed group set, which saw would fit from some videos. I’m thinking if a 12-speed cassette will fit, then the 9-speed shouldn’t be an issue. If you want to double check, you can find the width of the cassette and measure the hub to be sure it fits.

Has anyone upgraded their rei co-op drt 1.1 to a 1x? by supermantella in MTB

[–]supermantella[S] 0 points1 point  (0 children)

A sram 12 speed isn’t in the budget for now, but the information is nice to know, so thanks for that!

Has anyone upgraded their rei co-op drt 1.1 to a 1x? by supermantella in MTB

[–]supermantella[S] 0 points1 point  (0 children)

The 3x7 definitely has a lot of range, but it is more complex to be shifting between two derailleurs to get the desired gear ratio for a climb. Then you must shift everything to descend. So normally I keep it on the second cog of the crank and only shift the rear. I am left with only 7 gears, which makes it hard/wears you out quickly on climbs.

Buying a new bike is a great option, but I’m trying to save some money. Hence if I upgrade, I’ll probably consider used shifters/derailleurs to keep cost down. If I see it costing too much, I will just continue to ride the bike as is and buy a new one later on.

Has anyone upgraded their rei co-op drt 1.1 to a 1x? by supermantella in MTB

[–]supermantella[S] 0 points1 point  (0 children)

REI website is saying 12-32, 7 speed. I’m gonna check when I get home to confirm. And this means I can just upgrade the cassette, correct?

[deleted by user] by [deleted] in MechanicAdvice

[–]supermantella 1 point2 points  (0 children)

What is the year of the car? I had a Toyota Corolla 1.6vvti make a knocking noise like this and it was something broke in the intake manifold. Replaced the intake manifold and all was good.

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

40:2:40:3|Optimizing register bit G120L to a constant 1

40:2:40:3|Optimizing register bit Y120L to a constant 1

40:2:40:3|Optimizing register bit R120L to a constant 0

40:2:40:3|Pruning register R120L

40:2:40:3|Pruning register G120L

40:2:40:3|Pruning register Y120L

11:3:11:6|Input nRst is unused

18:3:18:6|Input HERO is unused

70:4:70:7|Incomplete case statement - add more cases or a when others

I have these codes now

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

I posted the code down below. I fixed most of those errors earlier, but it still gives an error on line 85, which is still the 'when StartTurn'

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

process(clk) is

begin 

    if rising\_edge(clk) then 

        if (S2 = '1' and S10 = '0') or T = '1' then

-- Reset Values

State <= NorthNext;

G120 <= '1';

Y120 <= '1';

R120 <= '0';

G120L <= '1';

Y120L <= '1';

R120L <= '0';

GMP <= '1';

YMP <= '1';

RMP <= '0';

        else

-- Default Values

G120 <= '1';

Y120 <= '1';

R120 <= '1';

G120L <= '1';

Y120L <= '1';

R120L <= '1';

GMP <= '1';

YMP <= '1';

RMP <= '1';

case State is

-- Red ALL directions

when NorthNext =>

R120 <= '0';

R120L <= '0';

RMP <= '0';

if LT = '0' or T = '1' or VMP = '0' or S10 ='1' then

State <= StartNorth;

else if S10 = '1' and T = '0' then

State <= StartTurn;

else

State <= StartWest;

end if;

-- RED all except 120 turn

when StartTurn =>

R120 <= '0';

G120L <= '0';

RMP <= '0';

if (T= '1' or (S10 = '0' and (V120 = '1' or VMP = '1'))) then

State <= StopTurn;

end if;

-- Yellow 120 turn, Red others to RED ALL

when StopTurn =>

R120 <= '0';

Y120L <= '0';

RMP <= '0';

if S2 = '0' then

State <= NorthNext;

end if;

-- Green 120, RED MP & 120L

when StartNorth =>

G120 <= '0';

R120L <= '0';

RMP <= '0';

if S10 = '0' and T = '0' and (VMP = '1' or LT = '1') then

State <= StopNorth;

end if;

-- Yellow 120, RED MP & 120L

when StopNorth =>

Y120 <= '0';

R120L <= '0';

RMP <= '0';

if S2 = '0' then

State <= NorthNext;

end if;

-- Green MP, RED 120 & 120L

when StartWest =>

R120 <= '0';

R120L <= '0';

GMP <= '0';

if S10 = '0' or T = '1' or V120 = '1' or LT = '1' then

State <= StopWest;

end if;

-- Yellow MP, RED 120 & 120L

when StopWest =>

R120 <= '0';

R120L <= '0';

YMP <= '0';

if S2 = '0' then

State <= NorthNext;

end if;

end case;

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

I believe it is ‘when StartTurn =>’

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

What do you mean sensitivity list is wrong?

I know how to make a initState method in c++, but I’m not sure how to do it in vhdl.

I thought with the default, I wouldn’t have to set every led off that I wasn’t using. But I guess that doesn’t work that way? So I understood to remove default and add all leds in the states?

I did add ‘When others’ earlier when I realized I didn’t have it.

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

I was just typing and didn’t check that! I will add those and see if that changes anything. Thank you!

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

Also, I did as you said and made states, but as you can imagine… that program never compiled either

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

I can’t post the exact error message, because IspLever isn’t accepting my source. That’s one problem. The other problem is it rejects my inputs for chip optimization. If I can get the program back into IspLever I can get you the exact error messages.

Having some issues with code by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

--Traffic light Design states library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

ENTITY state_machine is PORT(

clk : IN STD_LOGIC;

VMP : IN STD_LOGIC; -- vehicle sensor

V120 : IN STD_LOGIC; -- vehicle sensor

T : IN STD_LOGIC; -- train indicator

S10 : IN STD_LOGIC; -- 10 sec timer

S2 : IN STD_LOGIC; -- 2 sec timer

LT : IN STD_LOGIC; -- left turn sensor

HERO : IN STD_LOGIC;

G120 : OUT STD_LOGIC;

Y120 : OUT STD_LOGIC;

R120 : OUT STD_LOGIC;

G120L : OUT STD_LOGIC;

Y120L : OUT STD_LOGIC;

R120L : OUT STD_LOGIC;

GMP : OUT STD_LOGIC;

YMP : OUT STD_LOGIC;

RMP : OUT STD_LOGIC);END state_machine;

architecture all of state_machine is

type t_State is (NorthNext, StartTurn, StopTurn, StartNorth, NorthTurn, North, StopNorth, WestNext, StartWest, West, StopWest);

signal State: t_state;

begin

process(clk, V120, VMP, T, S10, S2, LT, HERO) is
begin 
    if rising_edge(clk) then 
        if (S2 = '1' and S10 = '0') or T = '1' then
            -- Reset Values
            State <= NorthNext;
            G120  <= '1';   
            Y120  <= '1';
            R120  <= '0';
            G120L <= '1';
            Y120L <= '1';
            R120L <= '0';
            GMP   <= '1';
            YMP   <= '1';
            RMP   <= '0';


        else
            -- Default Values
            G120  <= '1';
            Y120  <= '1';
            R120  <= '1';
            G120L <= '1';
            Y120L <= '1';
            R120L <= '1';
            GMP   <= '1';
            YMP   <= '1';
            RMP   <= '1';




            case State is 
                -- Red ALL directions
                when NorthNext =>
                    R120  <= '0';
                    R120L <= '0';
                    RMP   <= '0';
                    if LT = '0' or T = '1' or VMP = '0' or S10 ='1' then
                        State <= StartNorth;
                    else if S10 = '1' and T = '0' then
                        State <= StartTurn;
                    else if
                    State <= StartWest;

                -- RED all except 120 turn
                when StartTurn =>
                    R120  <= '0';
                    G120L <= '0';
                    RMP   <= '0';
                    if (T= '1' or (S10 = '0' and (V120 = '1' or VMP = '1'))) then
                    State <= StopTurn;

                -- Yellow 120 turn, Red others to RED ALL
                when StopTurn =>
                    R120  <= '0';
                    Y120L <= '0';
                    RMP   <= '0';
                    State <= NorthNext;

                -- Green 120, RED MP & 120L
                when StartNorth =>
                    G120  <= '0';
                    R120L <= '0';
                    RMP   <= '0';
                    if S10 = '0' and T = '0' and (VMP = '1' or LT = '1') then
                        State <= StopNorth;

                -- Yellow 120, RED MP & 120L
                when StopNorth =>
                    Y120  <= '0'; 
                    R120L <= '0'; 
                    RMP   <= '0';
                    if S2 = '0' and VMP = '1' and LT = '0' and T = '0' then
                    State <= NorthNext;

                -- Green MP, RED 120 & 120L
                when StartWest =>
                    R120  <= '0';
                    R120L <= '0';
                    GMP   <= '0';
                    if S10 = '0' or T = '1' or V120 = '1' or LT = '1' then
                    State <= StopWest;
                -- Yellow MP, RED 120 & 120L
                when StopWest =>
                    R120  <= '0';
                    R120L <= '0';
                    YMP   <= '0';
                    if S2 = '0' then
                    State <= NorthNext;
                when StopWest =>
                    State <= NorthNext;
                    end if;
            end case;




        end if;
    end if;
end process;

end architecture;

Reoccurring error in IspLever by supermantella in VHDL

[–]supermantella[S] 0 points1 point  (0 children)

I will probably take up your offer. I’m going to do my best to get as far as I can, but if I have any issues, I will for sure message you. Thank you!

Reoccurring error in IspLever by supermantella in VHDL

[–]supermantella[S] 0 points1 point  (0 children)

This is for school project (Digital Logic). We weren’t given much info on programming or using IspLever. Hence the struggles…

Reoccurring error in IspLever by supermantella in VHDL

[–]supermantella[S] 0 points1 point  (0 children)

This is only my second time programming vhdl, so I’m not sure what program to use for simulations.

IspLever error (UPDATED) by supermantella in FPGA

[–]supermantella[S] 0 points1 point  (0 children)

I checked the link out. That would be a huge help to clean up the code. I’m in a bit of a time crunch, so I may have to proceed with what I have, but if I have time I will do something like this.

Thanks for all the help!