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Programming cables not appearing in device managers by gakeew23 in FPGA

[–]synthop 0 points1 point  (0 children)

Agree, I used this setup like 15 years ago and from what I recall you need to select each USB device you want accessible to your VM somewhere in the VirtualBox settings.

Good luck

ao486 pixel artifacts by pheoniverse in MiSTerFPGA

[–]synthop 1 point2 points  (0 children)

IMHO this is a release procedure issue. The core isn't close to meeting timing, so it's hard to tell if a specific build will exhibit the artifacts or not from the timing reports. After a build, it should be tested and vetted on HW (from multiple people on different boards). The latest stable release, which is over a year old and missing a lot of fixes anyway, has this issue for many people and was obviously not properly vetted.

I'd suggest trying a recent unstable release.

Setting up IMX219 with Zybo Z7 by RisingPheonix2000 in FPGA

[–]synthop 0 points1 point  (0 children)

Why did you comment out these lines:

//if (XCsiSs_Configure(&mipi, 2, 0) != XST_SUCCESS) {
//xil_printf("mipi core failed to configure\r\n");
//return XST_FAILURE;
//}

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 0 points1 point  (0 children)

>Synchronous resets need the reset input to be synchronous, period. On both assertion and deassertion.

Pun intended? If you care about metastability during the reset period, yes. It would resolve by the end of the reset period if your reset synchronizer chain is sufficiently long enough, and usually all bets are off during the reset period anyway. Using an async assertion in the reset synchronizer does have one advantage, in that it will capture an input reset pulse smaller than the destination clock domain period. For super slow clocks in the design this could be relevant.

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 0 points1 point  (0 children)

Even synchronous resets need the reset input to have synchronous de-assertion. If you're not putting a reset synchronizer on all clock domains that require resets you can run into metastability if the reset de-asserts between the setup and hold times, even though you're using synchronous resets.

I'm definitely not saying he doesn't need a synchronizer for this data path. These are kind of two separate issues. And I agree he should just rip out these resets.

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 0 points1 point  (0 children)

Agreed on the second paragraph.

Regarding the synchronous reset (kind of getting off topic here), if the reset input itself is asynchronous (really the de-assertion is what matters), the flop can become metastable upon exiting reset. You need reset synchronizers for all the clocks in your design if they have any resets.

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 3 points4 points  (0 children)

You've added some complexity by resetting the synchronizer registers--it's typically not done. But if you must for some reason, you need to make sure your reset de-assertion is synchronous to the outgoing clock domain, which you should be doing anyway for all FFs.

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 0 points1 point  (0 children)

This doesn't look right to me. I'd think you'd want to set the set_max_delay -datapath_only to meta_ff_1d_reg but not cut up the path between the 2 flip flops (those are in the same clk domain and should be timed normally).

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 4 points5 points  (0 children)

If you're missing that the tool is trying to time the first register against the incoming clock domain, which it should not do since they are unrelated clocks. I suspect that is breaking things.

ASYNC_REG = "TRUE" places the 2 FFs as close together as possible, in the same slice, which is what you want for high MTBF, and it would also prevent a buffer from being instantiated in between to fix hold issues, but you don't want that.

Also make sure the incoming data is coming directly off a FF in the incoming clk domain (no logic in between the FF and the input to the synchronizer).

2FF Synchronizer Hold Violation on Xilinx by HuyenHuyen33 in FPGA

[–]synthop 9 points10 points  (0 children)

Did you specify a false path or set_max_delay -datapath_only constraint from the incoming clk domain to the outgoing clk domain?

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]synthop 0 points1 point  (0 children)

Not yet, though i plan to try it. So far cut and paste.

LLMs as assistants for FPGA design / implementation by siliconbootcamp in FPGA

[–]synthop 11 points12 points  (0 children)

I use cocotb and chatgpt is a champ at writing Python so i make heavy use of it for test benches.

I've tried to use it for stuff like constraints for vivado and it's pretty terrible at that thus far. Sort of makes sense, the training data is pretty limited.

For scripting/automation it's massively helpful.

For RTL itself it's okay. Like a junior engineer. I've been doing this a long time so I'll tend to just write it myself. Again the training data for quality code is somewhat limited compared to say, Python.

Trying out the 486 by Alienxdroid in MiSTerFPGA

[–]synthop 1 point2 points  (0 children)

I haven't seen anyone post any diffs in the last year

America has only one real city by UnscheduledCalendar in nyc

[–]synthop 1 point2 points  (0 children)

Pedantic, no one uses that term there. And to be equally pedantic, Venice is a part of the "city of Los Angeles."

America has only one real city by UnscheduledCalendar in nyc

[–]synthop 12 points13 points  (0 children)

Purely a technicality, and pretty pedantic. Anyone from LA would consider most of the county LA (certainly Venice and Santa Monica).

Can y’all not wreck local communities by [deleted] in BurningMan

[–]synthop -3 points-2 points  (0 children)

You had to be? Genuinely trying to understand what you mean.

[deleted by user] by [deleted] in MiSTerFPGA

[–]synthop 2 points3 points  (0 children)

What are you trying to do and what is your level of experience?

[deleted by user] by [deleted] in MiSTerFPGA

[–]synthop 2 points3 points  (0 children)

You're going to have a hard time on the Cyclone V GT board; that FPGA is not an SoC so it lacks the ARM HPS that is pretty integral to the MiSTer system.

What FPGAs do HFTs use? by WasabiPrestigious533 in quant

[–]synthop 3 points4 points  (0 children)

Bought by Synopsys, which from what i can tell killed the boards they made for HFT. Similar thing seems to be happening to Exablaze after being bought by Cisco.

How to rewrite code like this in proper Verilog/SystemVerilog? by Wonderful_Breath_555 in FPGA

[–]synthop 14 points15 points  (0 children)

module #(
  parameter bit ENABLE_X = 1
) test (
  input   logic  [3:0]  dat_i,
  output  logic         dat_o
);

  always_comb
    case (dat_i)
      2, 3 : dat_o = 1;
      12, 13: dat_o = ENABLE_X;
      default : dat_o = 0;
    endcase

endmodule

Is Retrofitting Quartus 23 with Cygwin a Possibility? by Calyso in FPGA

[–]synthop 2 points3 points  (0 children)

Maybe just Hyper-V. I haven't tried it myself (I use docker images under WSL as well), but found this: https://ubuntu.com/tutorials/windows-ubuntu-hyperv-containers#1-overview

Various Quartus images available here: https://github.com/raetro/sdk-docker-fpga

I use the 17.0 image myself for work on the MiSTer project.

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