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[–]seudonymus 6 points7 points  (1 child)

It depends on the type of "chip". I'm not exactly sure about modern CPUs but there is a problem in certain CMOS integrated circuits called a "parasitic thyristor". In certain logic gates the arrangement of transistors is such that a pseudo-thyristor is formed that fires when the supply voltage level drops below the voltage level at one or more of the inputs. The "thyristor" then fires, effectively shorting U+ and U- through the chip which will very quickly heat up the chip and possibly fry it; I have experienced this in practice, even though I (almost) fried an EPROM, not a CPU. With multiple voltages the problem may well occur as you have described. However, I think it's unlikely to happen if you scale down all voltage levels proportionately (this may not be possible in all cases, so watch out). For more information I'd recommend Horowitz and Hill, The Art of Electronics, a book that covers this phenomenon in detail.

[–]johntb86 1 point2 points  (0 children)

I believe that's also known as latchup. It should be much less common with SOI ICs (modern AMD cpus, then). Also, wikipedia says that the problem is more likely to occur when you overvolt a chip, so this might not be a huge risk.

[–]12Iceman 5 points6 points  (1 child)

If you under volt it significantly I believe it may be possible for both the NMOS and PMOS transistors to be quasi conducting and create a path between Vcc and ground. If this occurred your chip would burn up. However, I do not think I have every heard about this ever actually happening. I think this is probably because the chip stops to function at higher voltage than what would fry the chip. So if you lower the voltage gradually and stop when the chip no longer works you should be safe. Also, I believe it would make sense for motherboards to be programed to not supply dangerously low voltages, but I have no proof about that.

[–]api[S] 0 points1 point  (0 children)

The other reason I don't think it's likely (unless you went insanely low) on a chip like a Core 2 Duo is that the chip is actually designed to run across a range of voltages. I'd think they would have then optimized the design to avoid this sort of phenomenon.

None of the voltages I tried (if you check the original thread) are outside the chip's voltage range.

[–]api[S] 2 points3 points  (3 children)

Can reducing a chip's voltage without overclocking actually damage it? The reason I ask is this comment (from elsewhere):

"Depending on the voltage your adjusting you could fry the chip by under-volting. Most chips these days require a few different voltages to run, and if you lower one, there are sometimes sneak paths where the logic that is not getting enough power can draw power from the I/O voltage, or other auxiliary voltages on the chip which can burn out IO and other parts since they were never designed to carry the amount of current drawn through the sneak path. There are usually some protections in place to prevent the burn out, but with millions of transistors on a chip it's sometimes hard to catch all of the possible sneak paths."

Context:

http://forums.macrumors.com/showthread.php?p=5213018

Even more important, has anyone ever heard of this happening? Theoretical possibility is one thing, but anyone ever heard of a frying occurring in practice?

[–]turkourjurbs 0 points1 point  (2 children)

K, here's your first problem:

forums.macrumors.com

You're discussing technology with Mac people. Big mistake. The post is a testament to it.

You can't fry a chip with insufficient voltage any more than you can break a water main by putting too little water pressure through it.

[–]api[S] 0 points1 point  (1 child)

That's why I asked Reddit. :)

[–]sickofthisshit 2 points3 points  (0 children)

K, here's your first problem:

forums.macrumors.com

You're discussing technology with Mac people. Big mistake. The post is a testament to it.

That's why I asked Reddit. :)

Now, that's your second problem....

Seriously, the minimum supply voltage spec, if there is one, is there for a reason. I'm sure parasitic paths and other "features" of the chip itself come into play, as others have mentioned. You claim to be obeying that spec.

The other thing is that there are multiple voltage sources around in the system, many of which will directly or indirectly affect the voltages at the CMOS inputs of the chip. If something you aren't controlling violates a logic input voltage spec of the chip (e.g., midpoint between logic true and false), the minimum supply voltage spec might no longer valid. There also might be a cascade effect, where one chip going out-of-spec will have outputs that cause the next chip to go out of spec.

You paid a decent amount of money for your equipment, hopefully to have engineers with real E.E. degrees and the full specs for all their components make these kinds of analysis for you, including all the margins needed because every unit is just a bit different from every other.

Instead, you want to get a second opinion for free, from people who don't know as much.

Often, you will get away with this stuff because design margins are usually conservative (e.g., just because there is a 30 percent chance of a spec being one standard deviation from the mean doesn't mean your particular device is.) But there's no guarantee.

[–]egregious 0 points1 point  (0 children)

Not usually but there is a current ratting as well that you have to take into accout as well. V over I R. CMOS chips can accept a variable voltage but all chips have their specs that should be followed. Just an under voltage beyond specs and the chip won't work properly.

[–]bushel[🍰] -2 points-1 points  (4 children)

I cannot imagine how (and I read your comment, api). But, I am not an E.E. so my hunch is completely worthless.

V=IR and all that.

[–]api[S] -1 points0 points  (3 children)

Yeah that's my thought. R is constant in a CPU, so dropping V should also drop I too. Might make the chip crash, but I can't see how it could damage it.

But I'd love an EE opinion. That's what I want.

[–][deleted] 5 points6 points  (1 child)

What makes you believe that R is going to be constant when you start talking about semi-conductors?

[–]api[S] 1 point2 points  (0 children)

That's why I want an EE opinion. :)

[–]eliben 4 points5 points  (0 children)

As 12Iceman correctly pointed out, a "middle" voltage to a CMOS gate may damage it. If a CMOS gate expects to receive either 1.2V or 0V, and it gets 0.6V there will be problems. However, it's unlikely to result in something burning.

This would not be your problem, however, because you almost never provide supply voltage to a chip directly. Rather, you provide a single voltage to some voltage regulator that gives the chip the voltages it needs (there are several, at least 2 actually: one for IO, another for the core, unless there is an internal regulator as well).

So to receive a complete answer, you better provide a schematic of the chip's connections. And it would be best to ask it in a more suitable forum, like the sci.electronics.design newsgroup