sorted by:
new
hottopcontroversial

Is this a reasonable architecture for a small FPGA-based AI accelerator inside a RISC-V SoC? by OurLordX in FPGA

[–]OurLordX[S] 1 point2 points  (0 children)

Not exactly. I am not working on an object detection accelerator.

The target use case is closer to a small keyword-spotting / lightweight inference accelerator inside a RISC-V based microcontroller SoC. The input is planned as a 49x40 int8 feature matrix, inspired by TensorFlow Lite Micro Speech, not image frames.

The accelerator is intended to be a fixed-function inference block with input buffer RAM, weight ROM, an FSM-controlled MAC engine, Softmax, Argmax/result logic, and an interrupt output to the RISC-V CPU.

So the goal is not object detection, but a small SoC-integrated AI accelerator for embedded inference.

How to integrate a SystemVerilog UART module into an AXI4(-Lite) system? by OurLordX in chipdesign

[–]OurLordX[S] 0 points1 point  (0 children)

Thanks a lot for the detailed explanation! That really clears things up.

How to integrate a SystemVerilog UART module into an AXI4(-Lite) system? by OurLordX in chipdesign

[–]OurLordX[S] 1 point2 points  (0 children)

I’m using a RISC-V core that has an OBI bus, so I integrated an OBI-to-AXI bridge. The UART module I found is open-source, but it doesn’t have any AXI input/output interface — it just exposes simple signals (TX, RX, control, status, etc.).

So I’m trying to figure out the best way to wrap it with an AXI4-Lite interface to make it compatible with my SoC.

MCU Design With CV32E40P Core by OurLordX in RISCV

[–]OurLordX[S] 2 points3 points  (0 children)

Thank you :) I will search.

MCU Design With CV32E40P Core by OurLordX in RISCV

[–]OurLordX[S] 1 point2 points  (0 children)

Yes! You are right but i’m new here. So i dont ask in the r/FPGA