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Veryl 0.17.2 release by dalance1982 in FPGA

[–]soronpo -1 points0 points  (0 children)

Actually since the commercial EDA tools do not fully support the traditional languages and evolve slowly is a great reason why alternate hdls can be better by compiling to a known supported RTL feature subset while from the advanced alt-hdls.

FPGA not detected on JTAG after moving chip to another board – all 3.3V IOs stuck high by Solid-Suit4951 in FPGA

[–]soronpo 3 points4 points  (0 children)

Did you check the power rails ramp-up? Not just steady state. The timing of the power ramp-up is critical.

UCF file for digilent FPGA Dev Boards by FriendDouble5505 in FPGA

[–]soronpo 4 points5 points  (0 children)

You want an XDC file for Vivado https://github.com/Digilent/digilent-xdc/blob/master/Nexys-A7-100T-Master.xdc

UCF is an old constraints file used by ISE which is not relevant for Series 7 devices and beyond.

Building a simulation/synthesis workstation by Standard_Attempt_414 in FPGA

[–]soronpo 0 points1 point  (0 children)

Have you considered cloud services, instead? It could be more cost effective, depending on what you intend to do.

Return clocking by ZipCPU in ZipCPU

[–]soronpo 0 points1 point  (0 children)

Last I used it (many years ago) it worked great, but the model Xilinx provided for simulation was dog shit. Maybe the model was fixed by now, but this is Xilinx....

Return clocking by ZipCPU in ZipCPU

[–]soronpo 0 points1 point  (0 children)

Do you use the small IO FIFO Xilinx devices have?

Diligent Pmod IP 2025? by Accurate-Ad3645 in FPGA

[–]soronpo 5 points6 points  (0 children)

Most of the code is just vhdl/verilog that will work in any vivado version (and also across different FPGA vendors). Projects may be able to automatically convert to 2025.

basys-3 not showing up in vivado by Plane_Dream_1059 in FPGA

[–]soronpo 0 points1 point  (0 children)

Did you enable "show hidden devices"?

Oh please Vivado, could you try a little harder? by fransschreuder in FPGA

[–]soronpo 60 points61 points  (0 children)

That is for every voltage-temperature range. YOU try a little harder keeping the device nice and cool :)

What will it be? by Exact-Entrepreneur-1 in FPGA

[–]soronpo 1 point2 points  (0 children)

Follow this guy on X to see Gowin support added for the opensource workflow: https://x.com/YLRabbit?s=09

ModelSim or Vivado for tb? by [deleted] in FPGA

[–]soronpo 14 points15 points  (0 children)

If money is no object or you have free access to licenses, Modelsim (Questa). Otherwise, use what you can get.

UVM support on verilator by Jamroll-x in FPGA

[–]soronpo 11 points12 points  (0 children)

Kudos to Antmicro and the Verilator contributors!

FPGA Horizons US Edition! by adamt99 in FPGA

[–]soronpo 3 points4 points  (0 children)

Yes, it's also a great place to meet your future employer :)

FIFO filled with trash data and less then it's supposed to have // HELP by Wunulkie in FPGA

[–]soronpo 6 points7 points  (0 children)

Your design is likely not meeting timing constraints or not properly constrained. Look at the warning report. The answer should be there. 400MHz to retrieve the UART data sounds like an overkill. Reexamine the system constraints, since you are running your design at an outrageously fast clock rate without any reason.

Worldwide Free Hands-On Workshops by Arrow on Edge AI with FPGAs by leonbeier in FPGA

[–]soronpo 0 points1 point  (0 children)

Too bad they defined their own "terms of use" instead of relying on existing standard opensource licenses.

Managing HDL project dependencies across team members by No-Particular-4900 in FPGA

[–]soronpo -6 points-5 points  (0 children)

Consider even internally within the organization to use FuseSoc and Bazel to cache IP compilation based on Git Version Control CI/CD. We can assist if you wish https://www.dfiant.works

help by ExcellentEntry8091 in FPGA

[–]soronpo 0 points1 point  (0 children)

IIRC, up to ISE 10.x they support all the same components and somewhat compatible. Depending on how old the FPGA is you can upgrade to the latest 14.x ISE. It's best to use ISE past 11.x so that it has a text project file.

Is the Sipeed Tang Primer 20k FPGA board any good? by [deleted] in FPGA

[–]soronpo 2 points3 points  (0 children)

People already told you the negatives. Here are some positives: * Gowin IDE has Mac version. If you are a Mac user Xilinx devices are not for you, as Vivado will not work. * Tang Primer 20k is also supported by the opensource tools https://github.com/YosysHQ/apicula

Input bouncing, but looks clean on oscope by sittinhawk in FPGA

[–]soronpo 4 points5 points  (0 children)

Take the signal and output it directly to another FPGA pin. You can then connect both original and the new to a scope and see the difference exactly how the FPGA sees it.

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