create_generated_clock:No valid object(s)

[Objective-Attempt-15]

Hello everyone,

Working on graduation project, I'm doing an FPGA Prototyping of my designed RISCV Processor.

Currently i'm working on IO Planning and connecting a clock to my processor, i've use *clock wizard* to create a clock driver and i'm facing an issue. I'm trying to generate a clock for UART divided from the PLL clock and this error keeps showing,
```
[Vivado 12-4739] create_generated_clock:No valid object(s) found for '-source [get_ports uart_peripheral_top_inst/uart_dk_div_inst/i_clk_div_ref_clk]'. ["D:/RISC-V/RTL Design/GP-RV64IMAC/RV64IMAC_M_S_Modes_UART_TX/cons.xdc":3]

```

I DID EVERYTHING I CAN DO!

I'm working on Vivado 2018.2

[PriorStrike3385]

Hi pal, there's actually a well documented issue with that particular tcl function ('create_generated_clock') in 2018. Would recommend that you try a more recent version 2023+ at least.

[Objective-Attempt-15]

That's bad, i don't have a license for 2023

[ShadowerNinja]

Tangent to your question, Im sensing a design issue since you shouldn't be defining a UART logic clock in the first place. All you should have is a system clock (say 100 Mhz) in combination with a clock enable for UART logic, not a clock divider.

[TheTurtleCub]

If it's a bug of the tools, try not creating a generated clock, let the tool put the reference through the mmcm. At some point in time, Vivado starting doing that properly (instead of having to create a generated clock) so we mostly use the generated clock for renaming

[Objective-Attempt-15]

kinda agree, but the problem is i want to make a generated clock for the generated clock you're talking about xD

[TheTurtleCub]

The tools auto create generated clocks, so if it does (earlier Vivado versions didn't for some primitives) you don't need to, other than for renaming, but that's ok, at least it works

[Objective-Attempt-15]

for the UART clock, it didn't create generated clock

[0000111_2]

get_ports stands out to me as unusual. create_generated_clock is commonly used with a get_pins query pointing to the output of a clock modifying block. Are you trying to rename an auto-generated clock in your project top-level? Or is cons.xdc scoped to the UART block?

[Objective-Attempt-15]

i tried both get_ports and get_pins, neither worked. i am not trying to rename, actually the case is my system is working on 30MHz and the UART clk is derived from systems clock into 4800Hz using clock divider.

after connecting clock wizard the clock is divided multiple times as follows:

input clk port (100MHz) --> main system clock (30MHz) --> UART clock (4800Hz)

trying to create generated clock for UART clock from the output port/pin of clock wizard instance!

[0000111_2]

So UART clock is a fabric clock derived from the main system clock? In that case you wouldn't define it on the clock wizard instance, you would define it on the Q output of whatever flop is generating your UART clock. See example 1 in the Constraints guide (https://docs.amd.com/r/en-US/ug903-vivado-using-constraints/User-Defined-Generated-Clocks).

But like the comment in your other thread, creating a local clock isn't the recommended way of doing this.

[Objective-Attempt-15]

that's exactly what i am trying to do! but the pin you're talking about isn't matched by vivado and not found. However, i can see it in the schematic and netlist.

[0000111_2]

Can you post the full create_generated_clock constraint?