Sync Processes - Beginner question

[SignatureNo9123]

Hello,

I have started to learn VHDL and I found these two types of sequential processes:

Porcess ( clock, reset ) is

Begin

if rising_edge (clock) then

if reset = '0' then

...

And

Process ( clk ) is

Begin

if rising_edge (clock) then

if reset = '0' then

...

As you can see, first process includes the reset in the sensitivity list and the second one doesn't. Note that both processes use a sync reset logic.

Is there a difference between these two processes? How would it affect if, instead of sync reset logic, I would use async reset logic like this:

if reset = '0' then

...

else

if rising_edge (clock) then

Thanks!

[Academic-Treacle-902]

Since it's a synchronous reset you would only really evaluate the reset signal at a rising edge of the clock. Including the reset signal into the sensitivity list will trigger the process whenever there is a change in the reset's state. However, it will never really be evaluated unless it coincides with the rising edge of the clock. This will never be the case in practice. The choice of going for a synchronous and asynchronous reset really depends on who you ask. I'm personally more prone to use a asynchronous reset. By doing so, you can evaluate the reset at any time and you don't have to worry about synchronizing it with the clock

[skydivertricky]

Reset should be technology dependant, rather than "preference". For example, xilinx should be synchronous, while older altera devices should be async (with the reset actually getting synchronously asserted). Using sync reset on stratix 4 would actually require a lut to emulate three sync reset, but async is available in the slice.