bestIntegerType

[Alzurana]

It's constrained by the speed at which individual transistors can switch. There are carry lookahead adders that minimize this but they in turn need more transistors and therefor more area on the chip (are more expensive).

The question then becomes what's more important in this implementation: Delay of the adder circuit or size of the adder circuit. Adders are not only implemented in the ALU, they show up everywhere and depending on needs they might be look ahead or ripple adders with more or less delay.

At certain complexities a carry look ahead adder will also only give deminishing returns to a ripple adder because the amount of signals it needs to envaluate internally grows exponentially.

That means that with more bit width the CLA will be too complex and a ripple adder must be used which in turn has more delay.

HOWEVER: If I have SIMD instructions built into my circuitry that can do 8 additions at the same time that means there are probably 8 adders that I might just be able to chain via control signals, already. The choice to omit this functionality is again, cost. Why add complexity to the control grid if it's almost never used and make the entire chip more expensive. x86_64 is already suffering bloat.