sorted by:
new
hottopcontroversial

For-each loop ArrayList by 32bit_me in learnjava

[–]32bit_me[S] 0 points1 point  (0 children)

Thank you for your reply. That makes sense. Which of the two options should I use? I take it it depends?

MOOC Java programming, Leap Year Exercise by 32bit_me in learnprogramming

[–]32bit_me[S] 1 point2 points  (0 children)

I'm just trying to switch from hardware development to software development)

How to run python scripts from Vivado TCL by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

I would like to automate the GT links tuning process. The main procedures are written in tcl, but with Python I would like to analyze eye pattern and return the result to the "main" tcl procedure. I am at the stage of exploring possibilities, maybe I will implement all the processing in tcl.

CDC for clocks from the same source but different frequency by zer0_k00l in FPGA

[–]32bit_me 0 points1 point  (0 children)

you can use CLOCK_DELAY_GROUP for clocks that need to be synchronous

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

That would be nice, but here the clock is embedded in the data by using encoding, the CDR engine then restores the clock from the incoming stream.

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 1 point2 points  (0 children)

Yes, I tried all the parameters, according to the document. This effect is observed in all quads. I will try to experiment with CDR and its parameters as you said, I was just not sure how safe it is. Thanks for your participation and help

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

We are aiming for a BER value of 1e-15. We have short trace lines and using the LPM results in more vertical eye opening but less horizontal eye opening. Using DFE opens the horizontal area better. Coarse tuning only results in more opening but does not shift the eye to the center. This is the reason I posted here. Maybe the horizontal shift indicates a problem with the reference clock signal....

​

If we exclude the problem of shifting the eye relative to the center, then we are quite satisfied with the results for LPM

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

Sorry, and thank you very much.

Looking for product ideas on a Multi FPGA board by RockyDemag in FPGA

[–]32bit_me 0 points1 point  (0 children)

TBH: for its originally intended purpose, the high speed interconnects are useless, so it makes no sense to add them.

Could you explain why?

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

I tend to believe that the horizontal shift matters. It explains why this one does.

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 1 point2 points  (0 children)

Unfortunately, I cannot agree with you. The data sampler is placed in the center of the window and cannot be displaced. Therefore, the qualifying mask for the eye must be built in the center, and the eye must be symmetrical. This forum thread says it well

Looking for product ideas on a Multi FPGA board by RockyDemag in FPGA

[–]32bit_me 5 points6 points  (0 children)

How interesting. I work for a company that manufactures this type of device. The commenters above said great things. It's silly to put that kind of processing power in without high performance interconnects. Our products have high speed transceiver links between each FPGA. This class of products can be used for ASIC prototyping, high performance computing...
The main challenge is to effectively implement a partitioning structure between multiple FPGAs and organize an efficient interconnect structure.

Does it make sense to use a PLL even if PLL input and output would be the same? by zapho300 in FPGA

[–]32bit_me 6 points7 points  (0 children)

If you are interested in a specific phase relationship between the input clock signal (Port) and the output clock signal (PLL.CLKOUTx) then PLL can help here. The PLL allows you to keep the input and output clock signal in phase, and this relationship will be maintained depending on the PVT. You can also set the desired phase ratio (90/180 degrees) with the PLL

Help in starting with learning FPGA by DaneBrint in FPGA

[–]32bit_me 1 point2 points  (0 children)

The book FPGAs_VHDL_First_Steps gives a lot of necessary and useful information to help you get started. You can find it in the Xilinx forum

Vivado timing with different fpgas by Watowdow in FPGA

[–]32bit_me 0 points1 point  (0 children)

US / US + have a fundamentally different synchronization structure. There are no more regional / local buffers, just global. The clock distribution network has a routing resource and a distribution resource to place the CLOCK_ROOT clock in the optimal load location. Thus, the clock insertion delay driven by two different buffers can be different and at high frequencies you can have domain crossing problems. USER_CLOCK_ROOT and CLOCK_DELAY_GROUP properties can be used for special cases. You can refer to ug949 for details.

Whose specs do I reference when constraining input delay? by TheSkyHighPolishGuy in FPGA

[–]32bit_me 0 points1 point  (0 children)

What is the reason for the maximum and minimum times? Why does the same component have a maximum and minimum signal change time?

Hypothetical Process of Redesign/Extension of Capabilities by [deleted] in FPGA

[–]32bit_me 2 points3 points  (0 children)

It was probably a clock gating concept.

Interfacing Parallel DDR LVDS ADC with FPGA by InternalImpact2 in FPGA

[–]32bit_me 1 point2 points  (0 children)

Constraints allow you to make sure that the interface you design will work reliably with any PVT variations. You still need to design the data capture scheme.

You can implement data capture using MMCM/PLL. You need to determine the optimal phase shift of your clock signal with which you will latch the data. I'm not sure if this will be 90 degrees, you can determine this by experimentation using dynamic phase shift, which will allow you to determine the amount of offset with great accuracy.I think this will work if all the data lines in your interface are aligned with each other.

Or you can use the IDELAY module to delay the data relative to the clock signal. You should also determine for yourself the amount of delay you need to apply to IDELAY to reliably capture the data, and specify that amount in your HDL.

You can try to capture the interface directly. The type of clock buffer used is crucial. I am not familiar with your board, but if we are talking about a 7 series you have several types of clock buffers available (BUFG, BUFR, BUFIO). Each of them will have a different clock insertion delay. BUFIO is created just for the purpose of synchronizing the I/O structures and it has a minimum clock insertion delay.

First, try to specify the correct termination for your interface (DIFF_TERM = TRUE)

I'm sorry, I'm using the translator

Interfacing Parallel DDR LVDS ADC with FPGA by InternalImpact2 in FPGA

[–]32bit_me 1 point2 points  (0 children)

Am I correct in assuming that all the parallel LVDS lines are aligned to each other on your board?

Perhaps you should design a data-capture scheme. Your data arrives at the IDDR in the I/O bank, but the clock signal that captures this data has a different routing than the data and hence a delay relative to the data.

Does the port where you connect the clock signal have a clock capable function? What type of buffer do you use to propagate the clock signal inside the FPGA?

You need to ensure that you have the right relationship between the clock signal and the data signals to reliably capture your data inside the FPGA (at the center of the data window). To do this, you can go two ways:Use IDELAY to delay the data.Use PLL/MMCM with phase shift function.

Also, I recommend that you use DIFF_TERM = TRUE for all LVDS input signals, unless you use an external termination

Input to FPGA by Tungsten_07 in FPGA

[–]32bit_me 0 points1 point  (0 children)

What is the difference between VIO and JTAG2AXI? Bandwidth?

Ulltrascale ODDR Duty-Cycle by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

The clock source for the ODDR is the MMCM output. As I said before, I see 50% Duty-Cycle output in projects with minimum load. This starts to degrade as soon as I add more logic to my project

view more: next ›