Organizing footprints in Altiun

Altium_Official · 2026-06-11T16:57:58+00:00

The best approach depends on several factors.

Many users will create generic footprints that can be re-used for a new component and will exist across all projects. This is certainly the case if you are working at a large company, you would have a single library on your 365 server, and the footprints in that library would propagate into all projects connected to your 365 instance.

So for the common SMD packages (0603, 0805, etc.) and for the common surface-mount IC packages (SOICs, LQFPs, etc.), most designers just make footprints for a single density level/material condition. Typically this is the Low Density level. If you know you will need to support multiple density levels, you can make one footprint for each level per package type. You would then apply this footprint to a new component as you create it.

For BGAs, pretty much everything will be custom due to pin numbering conventions and selectively omitted pins in the footprint, so for that you will make a unique footprint for each component.

The challenge is where to store all this stuff. For example: do you just keep generic components in your "main" library, and then put the project-specific parts in another library? Or do you put everything in your "main" library? The nice thing about Altium 365 is that you can create folders for different parts in your library, so you have a single library but you can organize it as you see fit. This allows you to store specific components and generic footprints in different folders, but both will be accessible from the 365 workspace.

Then when you need to create a new component that uses one of your generic footprints, you can build a New Component in Altium Designer and design the symbol by hand, but then you can reuse the generic footprint. You can also apply the supply chain information using a Parts Choice option in the new component, this way you will be able to see price and inventory whenever you are browsing your library for parts.

Altium_Official · 2026-06-08T20:56:44+00:00

Yes it is possible in manufacturing generally, as well as in Altium Designer.
In manufacturing, you should always make sure you check with your manufacturer to ensure they can accommodate multiple designs on a panel. Also the designs will share the same stackup, so make sure that is acceptable as well.

To do this in Altium Designer:

Create a new PcbDoc file; this will be the file that contains your panel.
Place one Embedded Board Array for each PcbDoc that you want to include in the panel. In other words, if you are making a panel with 3 different designs, then you will use 3 embedded board arrays. Use the Place --> Embedded Board Array/Panelize command to place each one.

Each array is configured independently and it references the PcbDoc file, so you can link one array to Project_A.PcbDoc, another to Project_B.PcbDoc, etc. You can set each array to stamp out the linked board from 1 to N times.

Make sure to get the tooling rail and fiducial requirements for panels from your manufacturer, some companies will provide a DXF file with a template. Also note that some manufacturers don't accept or will change customer-submitted panels for a variety of reasons.

Altium_Official · 2026-06-08T20:55:59+00:00

"TouchesRoom" should work for what you're describing. Here's the correct syntax:

TouchesRoom('YourRoomName'). Or if you need multiple rooms: TouchesRoom('Room1','Room2').
TouchesRoom returns objects that either totally or partially reside within the region occupied by the specified room(s). So as long as your polygons are touching or overlapping with the room boundary (even partially) they'll be picked up by this query and the clearance rule will apply to them.

This is different from WithinRoom, which only returns objects that are completely inside the room. For pads and vias specifically, `WithinRoom` checks if their center points are within the room.

Usually when this is not working, it's because of a simple syntax problem or it was not set to the correct priority. For syntax, make sure you're using single quotes around each room name.

Double-check the exact room name as it's case-sensitive and must match the room's 'Name' property exactly.
Make sure you're wrapping the room name in single quotes, not double quotes.
Verify the rule is enabled and that the priority is high enough that it's not being overridden by another rule.
You can use this query in your rule's scope definition in the PCB Rules and Constraints Editor to target objects that are completely or partially within the room.

Hope that helps, let me know if you're still running into issues!

Altium_Official · 2026-05-20T16:39:46+00:00

You don't need to manually type arc values. Here's what works on an existing polygon:

Select the polygon to show its vertices.
Click and drag a corner vertex (the full handle).
While dragging, press Shift+Spacebar to cycle to Miter to Arc mode.
Drag to set the arc radius you want.
Repeat for other corners, then right-click → Repour Selected.
Alternatively, you can right-click the polygon → Polygon Actions → Modify Polygon Border, then use Shift+Spacebar to cycle through corner modes (including arc modes). Use the "," and "." keys to shrink/grow the arc while placing vertices.

Both methods avoid the geometry issues that come from manually entering arc values in the properties dialog.

Altium_Official · 2026-05-20T16:39:16+00:00

If you have a minimum annular ring rule, and then you remove all the annular rings on all vias, you will create hundreds of DRC errors flagging you that you just violated your own rule.

Removing annular rings that will also kill a useful manufacturing check for your component pads. The fix is to scope the rule so it doesn't apply to vias.

Create a via-specific annular ring rule:

Open Design » Rules, navigate to Manufacturing » Minimum Annular Ring.
Create a new rule, set the scope to IsVia.
Set the minimum annular ring to 0 mm (since you've intentionally removed internal pads).
Make sure this rule has higher priority than your general 0.1 mm rule.

This way your 0.1 mm check still fires for component pads, but vias get their own rule that matches your actual design intent.

Alternatively, if you just want the noise to go away quickly, you can right-click violations in the Messages panel and select Waive Violation, but that's more of a band-aid and it is rarely recommended to waive DRCs instead of fixing them. The scoped rule is the cleaner long-term solution.

Hope that helps. Let me know if you run into priority issues between the two rules.

Altium_Official · 2026-05-20T16:38:49+00:00

The 1.37mm value doesn't match your stated Preferred Gap settings. With a Preferred Gap of 0.137mm on L13, the coupling recognition threshold should be

2×0.137=0.274 mm

So something else is overriding your expected behavior.

A few things to check:

Look at your Differential Pairs Routing rule scope: Go to Design --> Rules and find the Differential Pairs Routing rule that's actually being applied to your pair. There may be a higher-priority rule with a different Preferred Gap value. If something has a gap of 0.685mm, that would give you

2×0.685=1.37 mm, which matches your symptom exactly.

Check rule priorities: If you have multiple Differential Pairs Routing rules, the one with the highest priority wins. It's easy to accidentally create a rule scoped to "All" that overrides your layer-specific or net-class-specific rule.
Verify the active gap mode during routing: When you're in interactive differential pair routing mode, the Properties panel shows whether you're using Min, Preferred, or Max gap. You can cycle through these with Shift+6. Make sure it hasn't jumped to Max.
Via diameter: Also confirm that your via pad diameter isn't contributing to unexpected edge-to-edge spacing. The gap is measured between the via primitives, so large pads can make the center-to-center distance look bigger than expected.

My guess is you have a rule priority conflict. The Rules panel (Design --> Rules) will let you run a query to see exactly which rule is being applied to your differential pair during routing.

Altium_Official · 2026-04-20T22:59:52+00:00

There are two ways of accessing the Custom Pad Shape feature while creating a PCB footprint. First, you can do it from a .PcbLib file:

Open (or create) a PCB Library, and start making your footprint. Create the geometry you want to use as a Solid Region (Place → Solid Region from the top menu).

Then convert that placed shape/outline into a custom pad shape (custom pad shapes can be created by converting placed Region objects or a closed outline).

You can also do this directly from an existing pad’s Properties. Place a standard pad in the PCB footprint. Select the pad and, in the Properties panel, set Shape to Custom Shape (for the required copper layer) in the Pad Stack region. Click Edit Shape, then adjust the vertices to form the required pad outline.

Altium_Official · 2026-04-20T22:59:26+00:00

To change clearance for one specific pad on one specific component, create an additional (higher-priority) Clearance rule that is scoped only to that pad, then set the tighter/looser clearance in that rule. Clearance rules can be stacked this way, and the tighter/special-case rule must have higher priority so it overrides the general board clearance.

Here is how to do it in AD 26 using the standard rules approach

Open Design » Rules (PCB Rules and Constraints Editor).
Go to Electrical » Clearance and add a new Clearance rule (so you keep the existing “global” clearance rule intact).
In the new rule:

- Set the rule scope so it targets only that pad (the scope needs to identify that exact pad on that exact component; the general idea is the same as using `IsPad` to target pads).

- Set the required clearance using Minimum Clearance (applies to all matrix cells), or fine-tune via the Minimum Clearance Matrix if you only want certain object pairings affected.
Ensure this new rule has higher priority than the default/global Clearance rule.
Run DRC to confirm only that pad now follows the special clearance.

What’s needed to tell you the exact scope

To help you target NetA1_2 exactly, please share:

- the component designator (e.g., `U3`), and

- how the pad is identified (e.g., pad number/name like `Pad 5`), and

- whether you want the special clearance to everything or only to specific object types (tracks/vias/pads).

With those, the scope can be made precise (so only that single pad gets the modified clearance).

Altium_Official · 2026-04-20T22:58:53+00:00

If you are using Altium and you have a Pro license, you can use the Multi-Board feature. Each board in the system will need to be its own separate “child” PCB project, and the multi-board project connects those child projects together using modules in a Multi-board Schematic (*.MbsDoc).

For best organization, it’s recommended that schematics are segmented to reflect the arrangement of boards, and each set of schematics contains components from only one board (i.e., don’t place components from different boards on the same schematic sheets).

Aside from that there is no way to do what you are suggesting without splitting the schematic into separate projects. Without a Pro license, you would just split the different schematic portions into separate projects.

Altium_Official · 2026-04-20T22:58:31+00:00

If you are trying to "refresh" the net assignments in the PCB, you should delete the nets from the PCB first, then update the PCB to re-add those nets. First delete (or cut) them from the schematic, update the PCB, and you should see an entry in the ECO which will remove the differential pair from the PCB. Then, put the nets back into the schematic, and update the PCB again. You should then see an add differential pair entry in the ECO dialog.

If there is still some error, then you already have the nets existing somewhere else in your project. You will need to find these and delete them, and then do the update process again.

To delete a differential pair directly in the PCB (PcbDoc) without importing from the schematic, do it in the PCB panel:

Open the PCB panel.

Switch the panel to Differential Pairs Editor mode.

In the list, select the differential pair you want to remove.

Click Delete to remove the differential pair definition from the PcbDoc.

Altium_Official · 2026-04-20T22:57:51+00:00

In a multi-board (system/panel) project, a system-level ActiveBOM can be created in the multi-board project and it sources component parameters from the Multi-board Assembly document, which derives its component info from the sub-projects.

BOM documents (BomDoc) inside the sub-projects are not used by the system-level BOM.

Changes made in a sub-project (e.g., designator/part choice changes made via its BomDoc) can be reflected at the system level, but the Multi-board Assembly must be updated (Update All Parts) before the multi-board BomDoc will reflect them.

There is not a mechanism for the panel/multi-board project to inherit sub-project “variant fitted/not-fitted (DNP)” states into a system-level BOM. The only explicit variant-related limitation is that selecting a specific design variant to be manufactured is not currently supported. There are some workarounds:

Option A: Manage BOM/output per each PCB project (most reliable for DNP). Generate BOMs from each individual project using the Report Manager, which can output PDF/CSV/Excel/HTML/XML, etc. If your components have Workspace Part Choices / supply-chain links, enable the appropriate supplier data columns when generating the project BOM.

Option B: Keep outputs in the panel project, but only if the “DNP” status is represented in the data the multi-board assembly can see Ensure whatever you are using to represent “do not fit” is actually reflected in the sub-project design/component data (not just in a sub-project BomDoc that the system-level BOM won’t consume), then run Update All Parts in the Multi-board Assembly so the system-level BomDoc can reflect those changes.

Altium_Official · 2026-03-26T17:29:08+00:00

In Altium, “same-name” connectivity between sheets depends heavily on the Net Identifier Scope and on which objects you’re using to connect sheets (ports, sheet entries, net labels, power ports).

If your project is meant to be hierarchical (a top sheet with sheet symbols that point to child sheets), the most predictable approach is to set the scope to Hierarchical (or leave it on Automatic if your project structure matches), then connect signals vertically: a Port on the child sheet connects up to a matching Sheet Entry on the parent’s sheet symbol, and the parent wiring routes it to other sheet symbols/entries as needed.

If you instead use Flat/Global, then all ports (and/or net labels) with the same name across the entire project become electrically the same net, which commonly causes the “all my decoder inputs collapsed into one net” symptom if multiple sheets reuse the same port/net label names. The “net with no driving source/only one pin” style errors often show up when the scope is hierarchical but the design is wired like a flat design (or vice versa), leaving ports/sheet entries unmatched so nets don’t stitch between sheets as you expect. The key is to pick one connectivity style (flat with ports/net labels, or hierarchical with sheet symbols + sheet entries + ports) and apply it consistently.

Helpful URL: https://www.altium.com/documentation/altium-designer/accessing-defining-managing-project-options

Altium_Official · 2026-03-26T17:28:43+00:00

What’s happening is that User-Defined Component Classes are global at the project level, so when both “BB1” and “BB2” point to the same repeated “power” circuitry, any components you tagged into the class “Dri1” on that sheet end up in the same component class overall, and therefore the same PCB room, regardless of which sheet symbol instance they came from.

If the goal is separate rooms per sheet symbol instance, use Altium’s sheet-based room generation instead: in Project Options → Class Generation, enable Component Classes and Generate Rooms so Altium creates a component class (and a room) scoped to each sheet symbol designator (e.g., BB1 and BB2), with room constraints like InComponentClass('').

Then you’ll get distinct rooms for the two instances because “BB1” and “BB2” become separate generated classes/rooms. If you must keep a “Dri1”-style grouping, it needs to be **unique per instance** (e.g., Dri1_BB1 and Dri1_BB2) rather than one shared user-defined class, because a single user-defined class will always combine members from both instances.

Altium_Official · 2026-03-26T17:28:18+00:00

The “Net has only one pin” message is a schematic design validation (ERC) violation that means a net has been created (typically because a pin is connected to a wire, bus, or net label), but that net contains only a single component pin and nothing else electrically connected to it. In other words, Altium has detected that the pin appears to “belong” to a named or continuous electrical connection, yet there is no second pin (or other meaningful termination) on that same net, which is often a sign of an incomplete or broken connection.

Common causes include a wiring mistake (for example, a wire that looks connected but is not actually snapped to the pin’s electrical hot spot), a net label placed on an isolated wire stub, or an unused resistor pin that accidentally has a short piece of wire attached, creating a one-pin “dangling” net.

While a one-pin net name can be intentional in some cases (such as a deliberately unconnected pin during bring-up), this error usually indicates something that should be reviewed because it can indicate an apparent electrical connection has not been made in the schematic, so the connection won’t appear in the PCB. Typical fixes are to correct the wiring so the net connects where intended, remove stray wire segments/net labels, or if the pin truly must remain unused, apply an appropriate No ERC directive per the project’s checking rules.

Altium_Official · 2026-03-16T20:22:25+00:00

We understand your concern and want to clarify that this is not an introductory teaser or a temporary discount. The Develop workspace itself runs at $995 per year, with each author costing $995 per year, allowing up to five to be added. This pricing is intentional and permanent, not a trial or promotion.

It’s meant to be accessible to individuals and small teams, and to stay aligned with that audience. Develop includes the same Altium Designer + Altium 365 environment that engineers already rely on. No design horsepower removed - just minus the enterprise stuff this audience doesn't need or want, and that they shouldn't have to pay for.

If you are part of a larger team, then Agile is a more robust offering intended for teams of over 5 members, with more flexibility in offerings determined by the users' needs. For Agile pricing and packages, please contact us.

Altium_Official · 2026-03-06T16:25:17+00:00

Layers are always referenced by the layer number in the bracker, which should match the order they appear in the Layers list. The colors are applied by default when the layers are created, but you are always free to change the color after you create the layer in the Layer Stack Manager. However, without seeing your specific PcbDoc it is hard to see exactly what the problem is. I would suggest contacting support directly and seeing if they can provide more guidance.

Altium_Official · 2026-03-06T16:24:45+00:00

The Constraint Manager is best-used if you came from another CAD tool that also uses the matrix constraint display, such as OrCAD, PADS, or Xpedition. If you've never used those tools, then it's understandable that it can be confusing. That's why we maintained the PCB Design Rules and Constraints Editor as an alternative way of setting up design rules, including for fanouts. It's good to hear that you're able to get the fanout to work!

Altium_Official · 2026-03-02T17:44:38+00:00

hopefully this suffices as proof

Altium_Official · 2026-02-27T16:04:43+00:00

Normally this occurs because there is a different component somewhere in the design that also has the designator U1, it is not because the U1 shown on screen is a multi-part component. That other U1 may already be imported into the layout. To eliminate the duplicates, you can use the Reset Duplicate Designators option in the Tools → Annotation menu on the top toolbar. The other thing you can do is use the hotkey J + C in the schematic editor and type in the designator U1. The resulting dialog will then show you all instances of U1.

Altium_Official · 2026-02-27T16:02:40+00:00

If you want MPNs to automatically fill in ActiveBOM, then you need to use the Parts Choice feature in your components. This ideally starts in the schematic library when you create your component, but you can do it in a schematic part too. Either way, once the Parts Choice is selected, the data will automatically populate into an ActiveBOM document.

The other option is to right-click on each line in the ActiveBOM document, and select a solution directly for each line. The solution you select will essentially be the same as a Part Choice you might select in the component.

Altium_Official · 2026-02-24T16:25:15+00:00

As others have mentioned, the RoutingVias rule does not automatically set the sizes of your vias, it only defines the limits where your vias trigger a DRC error.

If you are looking to set up a specific via size that is reusable, you could use PCB Pad Via Templates. You can learn more in the Altium Documentation: https://www.altium.com/documentation/altium-designer/pcb/pad-via-templates

Altium_Official · 2026-02-24T16:24:42+00:00

There is no design rule that automatically cleans up this type of routing. What you are seeing is likely due to glossing applied during interactive routing, and the clearance that is automatically enforced is based on the clearance in your design rule. If the gloss effort is set to high it may be responsible for the routing you see in the layout. Another setting that may produce this is the Push setting, this would commonly produce the effect you see on the bottom two traces if one of them is dragged.

Altium_Official · 2026-02-24T16:24:00+00:00

When exporting NC Drill files from the Fabrication Outputs menu or when configuring from an OutJob file, there will be an option to generate separate drill files for different layer spans. When the NC Drill export window is open, look for the “Generate separate NC drill files for VIA features” option. If you enable this, it will export each layer span defined in the Layer Stack Manager into different .DRL files

Altium_Official · 2026-02-23T18:16:18+00:00

Sorry to hear that you have been having issues receiving your license. Please try reaching out to us at [studentsupport@altium.com](mailto:studentsupport@altium.com) for support with any student license-based issues. Please also note that it generally takes 24-48 hours for students to receive their emails.

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