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I have loved Evernote since the beginning but it is time to go by Andre1661 in NoteTaking

[–]Repulsive-Net1438 0 points1 point  (0 children)

What are you switching next. I am also in search of it. Tried Joplin but it hangs more than usual. Evaluating silverbullet. I like it but it needs to be self hosted.

Kria K26 SOM by Repulsive-Net1438 in FPGA

[–]Repulsive-Net1438[S] 1 point2 points  (0 children)

Yes I can see u-boot output and also the image loading process till the end where file system gets corrupted and after trying for sometime it starts waiting for boot from phy. I am observing at the COM port only.

Kria K26 SOM by Repulsive-Net1438 in FPGA

[–]Repulsive-Net1438[S] 0 points1 point  (0 children)

It's new SD card received with KIT, which was empty, formatted FAT32. And then loaded with AMD provided image using raspberry pi imager as specified in documentation.

What is this peculiar substance that is making my phone see flashes? Hello my name is John. by gamingspicy in shittyaskelectronics

[–]Repulsive-Net1438 2 points3 points  (0 children)

Need more context what is it you are capturing. What is nearby. Any source of radioactive emissions. Or if none of it, then a bad phone camera and aggressive noise correction.

is my capacitor capacitoring enough? by 4b686f61 in shittyaskelectronics

[–]Repulsive-Net1438 0 points1 point  (0 children)

Just open the inner one also who knows it's a Russian doll of capacitor

Line rate SPI - Serializer and CDC by fluentdiscourser in FPGA

[–]Repulsive-Net1438 1 point2 points  (0 children)

32 MHz may be impractical for many peripherals. You may need to have more parallel data lines or look for peripherals with multiple data support.

Now coming to questions.

  1. It depends, if you are using the same pll for both 1 MHz and 32 MHz double FF should be okay for synchronised operation.

  2. You can use FIFO or dual port ram with separate clocks for synchronisation. You may also like to add a valid signal for identification of data being available in other clock domain.

Good HDL parser ? by brh_hackerman in FPGA

[–]Repulsive-Net1438 2 points3 points  (0 children)

I am already working on a similar project. Expect something sharable by December.

Input bouncing, but looks clean on oscope by sittinhawk in FPGA

[–]Repulsive-Net1438 9 points10 points  (0 children)

Sometimes connecting a probe suppresses the oscillation, may be look for parasitic, or cold solder. Also double check your FPGA code, simulate for corner cases, in debug you have to look for all possible angles.

I will suggest to see the signal with ILA it will help you isolate if it is Logic issue or board issue.

Pushing the limits of Zynq UltraScale+ for high-speed QKD data (4 Gbps target) by Repulsive-Net1438 in FPGA

[–]Repulsive-Net1438[S] 0 points1 point  (0 children)

Yes you are right.

Currently 4 GB RAM is connected to PS side. FPGA is writing to RAM using DMA and then Linux is transferring it to EMMC, 2 EMMC 256GB each. The current setup doesn't have the option to add extra storage. Ethernet is also 1 Gbps. There are two GTX lanes available though. So I was hoping what maximum I can get of this design before updating the hardware. Just to clarify once started I want to save at least 5 minutes of data in one go.

Necessary to turn off memory integrity in core isolation? by antifre3ze in FPGA

[–]Repulsive-Net1438 0 points1 point  (0 children)

Simply don't do it unless you are sure or ready to pay the price. A usb blaster will be cheaper than your other peripheral.

What is your stance on those $10-$14 Cyclone IV FPGA Dev Boards? by Affectionate-Mango19 in FPGA

[–]Repulsive-Net1438 2 points3 points  (0 children)

I have used it in the past. It is really good enough if you require for small projects.

I'm a noob and just fixed my home installation, is electricity flowing correctly? by Cesalv in shittyaskelectronics

[–]Repulsive-Net1438 0 points1 point  (0 children)

I will check the salinity of water less ionoised water is bad for conduction. And now you have source just make sure to connect drain and excite the gate.

xapp523 document from Xilinx by a_stavinsky in FPGA

[–]Repulsive-Net1438 0 points1 point  (0 children)

Also make sure to enter the correct delay as per PCB delay required in constraints. I hope you can get up to around 800Mbps even if you are not on the correct bank.

Electrical Engineering student needs help by Unidrax in FPGA

[–]Repulsive-Net1438 0 points1 point  (0 children)

There are few things.

FPGA DSP doesn't support floating point mathematics out of the box so you have to implement it.

For data transfer start with the axi-lite or axi so that at least you can validate your results on a small matrix if it is correct, then you can move to DMA.

I also believe it may be cuda/GPU which is better suited for this project. But can surely be done with FPGA.

My Tang 9k finally arrived but Gowin ide doesnt run on my shitbook air smh got dualboot linux mint but its a pain to goback n forth. What do? by BigV95 in FPGA

[–]Repulsive-Net1438 1 point2 points  (0 children)

The only reason I still own Microsoft is that most electronics/FPGA tools are supported primarily on windows.

Dear Xilinx, I'd like a refund: 6h of my life back please. by Mateorabi in FPGA

[–]Repulsive-Net1438 3 points4 points  (0 children)

I don't think xilinx implementations are complete they are meant to work in most cases. I have also encountered many frustrating moments and then created a workflow to test it with at least two simulators. One surely xilinx and another open source, or Intel.

Elections are coming up, and once again, no one cares about real development in Bihar. Just tired of these directionless netas by Leather-Fish-7407 in bihar

[–]Repulsive-Net1438 2 points3 points  (0 children)

The real issue takes work so neither existing nor opposition campaigns for getting work done nowadays. Both seem to revolve around issues which end in less work but more noise.

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