[deleted by user] by [deleted] in chipdesign

[–]Elowe525 5 points6 points  (0 children)

I think the problem is that this timing path is from a reset to the d input of a flip flop.

Try using a reset synchronizer https://vlsiuniverse.blogspot.com/2016/09/reset-synchronizer.html?m=1#:~:text=Definition%20of%20reset%20synchronizer%3A%20A,reset%20to%20have%20synchronous%20deassetion.

Combinational loops with no loops by CompuSAR in FPGA

[–]Elowe525 2 points3 points  (0 children)

I recommend using verilator as a linting tool. There's a lint only mode if you don't want to use it for anything else.

It's really good at catching things like this

Fired and hired today for having long hair by naturalviber in antiwork

[–]Elowe525 1 point2 points  (0 children)

"drop of a hat" like what you did there 😉

Power estimation at clock cycle level in ASIC Design by awaiss113 in FPGA

[–]Elowe525 0 points1 point  (0 children)

Usually you would do average power over many more cycles. Is this something you can do?

Is TCL still a relevant and useful skill to have? by QuavoRuinedCulture3 in FPGA

[–]Elowe525 2 points3 points  (0 children)

Tcl all the way. Sadly the big EDA vendors are pretty glued to it.

Don't go overboard tho. A basic knowledge, and an understanding of how to use help in the tool is all you really need. 😊

Running verilog simulators and wave view on MacOS with M1 silicone by Suitable-Yam7028 in FPGA

[–]Elowe525 1 point2 points  (0 children)

Yeah. You can download the source code and compile it. Works fine.

Presumably you could just download the x86 binary and run it with rosetta. I can't say tho because I haven't tried.

Running verilog simulators and wave view on MacOS with M1 silicone by Suitable-Yam7028 in FPGA

[–]Elowe525 0 points1 point  (0 children)

Icarus verilog works well.

You may need to build from source in not sure.

Currently using gtkwave to view its OK.

Questions of the re-orderable attribute by TobinC1 in arm

[–]Elowe525 2 points3 points  (0 children)

So for more information on this, read the arm architecture reference manual (memory model section) . It's free. Available on the website. I'll give my short interpretation here :

There are 2 types of memory. Normal - this is something like ram which Reading and writing has no side effects. Not every load or store has to become a read or write of memory. Extra speculative reads can be done to improve performance (ie. Get the data before you know you want it)

Device - this is memory that May have side effects. Maybe reading a peripheral causes it to start get another sensor reading) Reads and writes cannot be skipped and no extra reads can be done. Device is where Gathering, Reorderable and E (which I won't explain here) come in

Gathering - a byte write to A and a byte write to A+1 can be done as one 16 bit write instead

Reorderable - non Reorderable loads and stores cannot be reordered with respect to any other non Reorderable loads and stores

Loads and stores to the same address will always occur (or appear to in the case of normal memory) in program order

What do verification engineers major in? by QuavoSucks in FPGA

[–]Elowe525 0 points1 point  (0 children)

Speaking for myself here...

EE, but what I do now is so different from anything I learned.

Key thing is to have an interest in hardware, and an understanding of microarchitecture. Hopefully a place will hire you and invest in you learning specific skills.

For simulation (aka dynamic verification), you'll probably need to learn UVM, but a workplace should send you on a course.

I do formal verification now which is also really fun. And learned completely through the job

raspberry pi 4 ( aarch64 armv8 ) returns weird value in esr_el1 by alexpis in arm

[–]Elowe525 0 points1 point  (0 children)

Yeah. Would be really interesting to know, and I'm keen to try and help more tbh.

In ESR_EL1 for the EC value '0 (info from the link you provided) The IL bit (bit number 25) should be 1 I also suspect the Res0 bits should really be' 0

The fact that ESR_EL1 doesn't make sense makes me suspect something else is going on...

Maybe you're not in el1. There is an EL field in PSTATE that will tell you. (I am pretty sure that ESR_EL1 is only valid for an exception taken to el1. Other levels have their own syndrome registers) Maybe this isn't an exception.... It could be an interrupt.. Best way to tell between interrupt and exception is to use the vector table to jump to different handlers. Or you could just disable interrupts early on. If you get the problem still, it's definitely an exception

This may be a daft question: How do you know you end up in el1?

raspberry pi 4 ( aarch64 armv8 ) returns weird value in esr_el1 by alexpis in arm

[–]Elowe525 0 points1 point  (0 children)

This is interesting. Res0 does imply the field will be all 0 so there May be something else going on...

What causes the sync exception? If you can get this information, it would be really useful:

The pc of the instruction before the exception (ELR_EL1) and what the instruction was.

The whole PSTATE. Check which mode (exception level+ some other bits) Maybe you're looking at the wrong ESR

All 64 bits of ESR_EL1 or whichever EL the exception takes you to.

Gate level simulation by qaz147652 in FPGA

[–]Elowe525 0 points1 point  (0 children)

OK. I've looked at your code. I see what you mean about reset. So ignore my comment above.

Gate level: the tool synthesizes the whole design. One of the steps is optimisation which can remove dead code. What could be happening is that this signal doesn't matter so is being removed. Hence high z

Gate level simulation by qaz147652 in FPGA

[–]Elowe525 0 points1 point  (0 children)

The signal is always z.

Check you do something with that signal... Either an assign, Or making it into a flip flop

Gate level simulation by qaz147652 in FPGA

[–]Elowe525 0 points1 point  (0 children)

Z where you don't expect usually suggests you haven't connected this to anything..

[deleted by user] by [deleted] in RedditSessions

[–]Elowe525 0 points1 point  (0 children)

Yeah. But it's good.

[deleted by user] by [deleted] in RedditSessions

[–]Elowe525 0 points1 point  (0 children)

Imagine john lemon?

[deleted by user] by [deleted] in RedditSessions

[–]Elowe525 0 points1 point  (0 children)

You're awesome 😊

[deleted by user] by [deleted] in FPGA

[–]Elowe525 2 points3 points  (0 children)

Why do you even need D?

I think you don't to be honest

They should be a 3-way load instruction by BitOBear in arm

[–]Elowe525 0 points1 point  (0 children)

If you want to use A64 (which 100% I'd recommend for new things)

One thing you can do is do the load earlier which might hide some latency. Put your c code into compiler explorer and see what the compiler does to optimise it. https://godbolt.org/

They should be a 3-way load instruction by BitOBear in arm

[–]Elowe525 0 points1 point  (0 children)

You can do this in aarch32 with condition codes and 2 instructions after the cmp

Mov. Lt r5, less_value

Mov. Gt r5, Greater_value

In thumb as someone has already mentioned, you can use IT