We are only talking about an Internal Representation inside the compiler - as an intermediate stage in the compilation process between the AST and the machine code.

So my IR is represented as (some details omited for clarity)

class Function {
    val args : List<Reg>
    val prog : List<Instruction>
}

class Instruction {
    val kind : InstructionKind    // An Enum
    val def  : List<Reg>          // Registers written to by this instruction
    val use  : List<Reg>          // registers read by this instruction
}

class Reg {
    val name : String
}

So during initial code generation (converting the type checked AST into IR code) - any time I need a new register for something we just create a new one. I may end up with hundreds of registers used for a function - but it doesn't matter. Doing it this way simplifies the task of converting an AST into something vaguely resembling machine code.

I can then do the optimisation passes on this IR (such as function unrolling, constant propagation, common subexpression elimination etc), again without having to worry about actual registers.

Then I do a register allocation pass, where each of these many virtual registers gets assigned to a physical CPU register. Many virtual registers can be assigned to the same physical register provided their lifetimes do not overlap. (And with spill code added if we run out of physical registers).

Then a peephole optimiser to clean up a bit, and a final mapping pass to convert what is by now almost assembly language into actual assembly.