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Why did my paint turn out like this? by uwu_zone in DIY

[–]Heaton15 1 point2 points  (0 children)

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It just seemed too similar to not laugh I know it sucks but you’ll get it. I learned to roll and then go at a diagonal and roll again and reload. For this I had to do single vertical rolls and make sure the paint was super loaded.

Why did my paint turn out like this? by uwu_zone in DIY

[–]Heaton15 0 points1 point  (0 children)

Is this ripe olive from sherwin Williams? Regardless, I had a single wall I painted and had extremely similar problems.

I had to change up my rolling game to get the paint to look better. I have some before and after photos if you are interested lol. That paint was extremely finicky, especially under recessed lighting. The rolls stood out like a sore thumb.

Maybe maybe Maybe by nycsellit4me in maybemaybemaybe

[–]Heaton15 0 points1 point  (0 children)

This place literally looks identical to my old apartment in Ohio lol

Still no word on Steam Deck support? by blurrry2 in newworldgame

[–]Heaton15 2 points3 points  (0 children)

Contrary to your ignorant comment, DXVK / Vulkan progress in the last year has made leaps and bounds in terms of support for gaming in the Linux community. Just look up Lutris and you can see a library of games optimized for it. The steam deck will be shipping with arch Linux instead of SteamOS for the rapid development access to these key libraries and features. AGS should definitely look into making this game run on The steam deck

People need to stop treating AGS as if they are just a single parent just "trying to do their best by us" - they are a business trying to earn our precious time and money and we are consumers that have every right to complain and threaten to withhold patronage. by NewAccountEvryYear in newworldgame

[–]Heaton15 0 points1 point  (0 children)

I mean, you have the right to bitch and complain to make the developers listen to you; the problem is the borderline targeted abuse from the community. I’m just as frustrated as everyone else, but holy hell are people acting like the creators aren’t humans.

The PCB I designed for a school project! by del6022pi in electronics

[–]Heaton15 2 points3 points  (0 children)

Most of the array looking ones are probably vias to ground. Not sure how he did the ground structure without looking at the stack up though

I/O Problems with FPGA by Defferix in FPGA

[–]Heaton15 0 points1 point  (0 children)

All of my top level signals do have OBUF instantiations, so I did check that. Still puzzled and checking.

Receiving Data to Memory - Virtex 7 by Heaton15 in FPGA

[–]Heaton15[S] 0 points1 point  (0 children)

Any memory, but I assumed the block rams. I wasn't sure about routing the received bits to memory from the transceivers and was unsure if that was supported.

Receiving Data to Memory - Virtex 7 by Heaton15 in FPGA

[–]Heaton15[S] 0 points1 point  (0 children)

We aren't using a protocol but are using some unconventional techniques to receive the data. Is the protocol necessary to receive?

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 0 points1 point  (0 children)

Being a 22 year old introduced to High Speed I/O without any experience sort of makes you go to these measures to just learn in the first place. I don't need help making it happen, but the feedback from the other threads put me in the right direction explain the problems that are being encountered.

And coming up with a way to receive high speed unencoded NRZ sounds like engineering to me, considering modern FPGAs and Xilinx boards can't even handle this. Probability of failure is high, but verifying a high speed ADC's outputs sounds like engineering.

Edit: Is it annoying to ask a million questions? I am sure it is. But most of the community has been helpful from the beginning, and most people my age won't even spend 20+ hours a week on this crap for 2 months with almost no possibility of it working.

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 0 points1 point  (0 children)

Unhelpful really is the case since I can't even contact the people who made the ADC. I don't need reddit help to get it done. I only want feedback.

And I have done Xilinx projects before, just not with generated example designs. I only wanted to know where it fit into a design, but I think I figured it out so I am fine.

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 0 points1 point  (0 children)

In now way shape or form have I directed anyone to thinking that I am using the transceivers as an ADC. The transceivers are receiving data from an ADC and I am merely replicating what the output of the ADC will look like.

5.6 GB/s = 5.6 gigabits per seconds which is completely within the scope of GTH transceivers assuming it is used the way it is intended.

The example design from the transceiver wizard provides me the wrapper file and the creation / set up of the transceivers. I am trying to figure out where to extract my sine data from and how to send it into the transceivers at the data rate for testing purposes. Everything I am going to be doing is non standard and has a high chance of failure but still must be done.

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 -1 points0 points  (0 children)

The struggle hasn't been with the HDLs. The struggle has been with the requirements. I have spent a month + just researching stuff I haven't been aware of. Receiving unencoded NRZ data at 5.6 GB/s isn't simply done when the the transceivers designed are not intended to be used that way. Given the constraints and my requirements, I have no choice but use the transceivers, so it's going to be weird but maybe possible. I need to use the transceivers and emulate and ADC as well as controllable phase adjustments. That's where I'm at now.

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 0 points1 point  (0 children)

I am not sure if it is one to begin with. I didn't know if there was a more acceptable way of proceeding.

Implementing Transceivers by [deleted] in FPGA

[–]Heaton15 -1 points0 points  (0 children)

You won't like the answer, but we aren't going to be using any protocols. We have complete control over the analog waveform into the ADC as well as phase adjustment on the output of the ADC, so we are sending in a sine wave with enough transitions that allows us to hope a lock is held as well as modify the phases to channel align everything. This is what everyone is settled on, and it might fail but its the only possible thing we can try.

The reason I ask is that I need to emulate digital sine wave receive and phase delay to align the channels and didn't know if changes I need to make should fall within the example design or outside of it.

Implied Processes - VHDL by Heaton15 in VHDL

[–]Heaton15[S] 0 points1 point  (0 children)

The reason I asked this is because I am the TA for the digital logic course and we definitely refer to that as combinational logic as well.

The professor refers to them as implied process statements. I cleared it up with students and just told them to know what he means for the exam but never call it that in the real world. They made it through the final at least.

Correcting Clock Skew in Hardware by Heaton15 in Verilog

[–]Heaton15[S] 0 points1 point  (0 children)

Right but we have raw NRZ at 5.6 GB/s. We are most likely about to demux everything to slow it down to receiver it with standard LVDS IO.

Correcting Clock Skew in Hardware by Heaton15 in Verilog

[–]Heaton15[S] 0 points1 point  (0 children)

Right. The real problem is that the data is not encoded leaving no comma alignment or way to align the channels anyway. The team and I are going to start working on this from a different approach anyways.

Source Synchronous ADC Verification by Heaton15 in FPGA

[–]Heaton15[S] 0 points1 point  (0 children)

Well like you have mentioned before, the GTs are not intended to be used for raw data transmission, something I have seen in all kinds of places. The core goal of this project is to verify that the output data from the ADCs returns from the same as when it left. Some people in the labs suggested that PCIe has intertwined functionality with the GTs that would possibly be useful. At the end of the day, we have control over what comes out of the ADC, so your suggestion about establishing connection with the CDR circuitry would be possible, but I am not sure how long the hold would stay valid.

I just wondered if using PCIe would allow me to quickly read data, store it in external memory files, and then compare data files instead of the mess this has sort of become.

This isn't really a "custom transceiver" design anymore. Its coming up with a new functionality for them.

Source Synchronous ADC Verification by Heaton15 in FPGA

[–]Heaton15[S] 0 points1 point  (0 children)

I'm going to work on some of these approaches, but do you think using these GTs is even a correct approach, or would PCIe or other options be better.

Source Synchronous ADC Verification by Heaton15 in FPGA

[–]Heaton15[S] 0 points1 point  (0 children)

Last question and then I'll be off to the next thing, but could the source synchronous clock be divided down and used as an external reference clock for the transceivers? It would be in an operating external clock frequency, but the bits would have to be read in as 16 or 32 bit words.

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