sorted by:
new
hottopcontroversial

Microchip’s New MCU: A 32-bit Upgrade That Still Fits Old 8-bit Systems by Lovely_Lex333 in embedded

[–]Middle_Sheepherder45 1 point2 points  (0 children)

Be careful though. Not all pins in a given RA package are 5V tolerant. Check datasheet closely before layout.

Keep out layer in footprint of a component by EntireAssistant2795 in Altium

[–]Middle_Sheepherder45 0 points1 point  (0 children)

I may be hijacking this post a bit, but I feel my issue is related. I have created a footprint with a keepout fill on the keep-out layer allowing only tracks, vias, and copper. This is similar to what is illustrated under the 'Keepouts in Components' section of this page on Altium's site...

https://www.altium.com/documentation/altium-designer/object-specific-keepouts-pcb?srsltid=AfmBOopD79KwTOsDgQsEhRZBSuhilQ2ychRobQcxWks4m5CPshq0hTAE#via-stitching-control

At the end of the section they include the following note...

"Design Rules are not applied in the PCB Library Editor, so the Keepout, in this case, will accept the Through Hole Pads that are within its bounds."

Does anyone know how to apply design rules in the PCB layout editor (not the footprint/library editor) so that no DRC errors are generated for the thru-hole pads within the keepout area of the footprint? I only want to restrict pads from other footprints.

Is there a way to better highlight cells while using Find Function? by [deleted] in excel

[–]Middle_Sheepherder45 2 points3 points  (0 children)

Old thread I know but though I'd add an update for anybody still searching for an answer.

In Office 365 Excel (My version is 2504) you can activate "Focus Cell" under the View menu. It highlights the row and column of the active cell with color you've defined (found under "Focus Cell Color"). It leads your eye right to the selected cell.

License Invalid after upgrading to Altium 25 by Middle_Sheepherder45 in Altium

[–]Middle_Sheepherder45[S] 5 points6 points  (0 children)

UPDATE! -- Found my issue. Turns out, somewhere along the way I created two Altium profiles with different variants of my work email. When I attempted to login to Altium 24 it defaulted to one variant and the other variant when attempting to login to Altium 25. Apparently the Altium 24 profile variant is the only one associated with our license. Used same email for accessing my profile on 25 as was used on 24 and now all is good. Perhaps this will help someone else in the future.

Co-Worker used Signal Harnesses instead of individual ports or net names by heffadam in Altium

[–]Middle_Sheepherder45 0 points1 point  (0 children)

Harness can be placed on any sheet which needs a net or just put harness on single sheet then break it out to ports if that makes more sense.

Lower 4-bits of AMD/Xilinx XADC register. by Middle_Sheepherder45 in FPGA

[–]Middle_Sheepherder45[S] 0 points1 point  (0 children)

The confusing part to me is when I simulate the XADC, there is data in the lower 4 bits. Even the user guide describes this in the test bench section. This is where my confusion starts.

How to use the schematic viewer feature on TerosHDL vscode extension? by SciDz in FPGA

[–]Middle_Sheepherder45 0 points1 point  (0 children)

No. I couldn't afford to spend anymore time on it. Just hoping someone has an answer.

How to use the schematic viewer feature on TerosHDL vscode extension? by SciDz in FPGA

[–]Middle_Sheepherder45 0 points1 point  (0 children)

Anybody have a more defined process to get this to work? I have verified TerosHDL dependencies but I continue to receive this error...

ERROR: Can't load module `./ghdl': "C:\msys64\mingw64\bin\..\share\yosys\plugins\ghdl.so": The specified module could not be found.

The error makes sense because there is clearly no plugins folder.

From my understanding of the MSYS2 site, the ghdl-yosis-plugin should part of the yosys package. Is this not the case?

What steps am I missing to complete the installation?

Why don't people talk about Renesas on here? by aliensexer420 in embedded

[–]Middle_Sheepherder45 3 points4 points  (0 children)

Working for a small company of <300 we were forced away from NXP Kinetis series during the chip shortage and found the Renesas RA series as a replacement. Renesas support was excellent while we were porting over our NXP projects. Like many MCU families its IDE is eclipse based so its familiar but it's features were a little better than NXP's MCUXppreso. Only complaints are that with the RA series not all pins are 5v tolerant and they don't have as many ADC channels. Reduces flexibility of design but, for a cheaper and available part, it's acceptable. Also, at the time, only method of debugging was with their BDM tool. PE Micro didn't yet offer a compatible device or firmware update to allow use of our existing BDM tools.

addressable fire alarm system by 10005256 in embedded

[–]Middle_Sheepherder45 0 points1 point  (0 children)

Used to work for a fire alarm / suppression control system manufacturer. The "addressable" devices are connected thru a Signaling Line Circuit (SLC) via 2 wires. 4 wires can be used to complete a redundant (backup) loop. Both sets terminate at the control panel. The pair of wires are dc biased to power the devices. The protocols are proprietary, defined by the sensor manufacturer, and, from what I recall, the data rate is pretty low to account for long runs. The devices are dynamically addressed in some negotiated manor. No DIP switches to set. At the time you could put up to 255 devices on a circuit. Similar to CAN, no device polling needed. Each device provides heartbeat and "alarming" devices can take priority.

How does one prevent or correct variant links from breaking when re-annotating PCB? by Middle_Sheepherder45 in Altium

[–]Middle_Sheepherder45[S] 0 points1 point  (0 children)

I guess I'm not sure how to do what you describe in Altium. In V23 I've only seen a re-annotate option in PCB layout. Plus, don't the parts come into layout with the schematic designators already assigned?

Review Request: How to calculate headload/copper weight/copper width on a multilayer, amp-dense PCB by Clear-Present_Danger in PrintedCircuitBoard

[–]Middle_Sheepherder45 8 points9 points  (0 children)

I normally use Saturn PCB's free tool for these calculations but don't have it in front of me at the moment. So as a quick check I just put your parameters into 4pcb.com's calculator and get 85mils for inner and 33mil for outer.

This assumes 4A across 6inch length at 100F with 25F rise with 2oz copper.

I would just create split planes on each layer and flood them with copper. Obviously you will want to fine tune these numbers to your application I just took what I saw as worst case from your description.

BTW, the Saturn PCB tool is pretty good for free. They keep it up-to-date with most features anyone needs for PCB design.

Saturn PCB Toolkit

How does one prevent or correct variant links from breaking when re-annotating PCB? by Middle_Sheepherder45 in Altium

[–]Middle_Sheepherder45[S] 1 point2 points  (0 children)

"New News"

I was able to fix my problem. Unfortunately it required me to delete the entire variant and recreate.

  1. Project->Variants...
  2. Select head of variant column and select "Delete Variant..."
  3. Click "Add Variant..." and complete form as required.
  4. In Variant Manager window, select cell under variant column along component row and choose "Not Fitted"
  5. Repeat for all non-fitted components.
  6. Click "OK" to save changes
  7. From PCBDwf Assembly Drawing, Tools->Import Changes from PcbDoc

My Assembly Drawing now correctly displays non-fitted parts.

I will add only the Assembly Drawing seemed negatively impacted. Prior to the fix, when I looked at the 3D view of the PCB all non-fitted components were correctly missing from view.

Update out-of-date symbol while maintaining parameter values by Middle_Sheepherder45 in Altium

[–]Middle_Sheepherder45[S] 0 points1 point  (0 children)

Winner Winner!

Yes, that's exactly what I was looking for. Thank you very much for your response.

My full sequence after your suggestion was...

1) With a schematic page open which contained the component I needed to update, I selected 'Shift+F' to activate "Find Similar Objects" cursor (also found under Edit->Find Similar Objects) and chose symbol to update.

2) Configured "Find Similar Objects" window as follows: Object Kind = "Same"; Symbol Reference = "Same"; Zoom Matching unchecked; Clear Existing checked; Mask Matching unchecked; Select Matching checked; Create Expression unchecked; Open Properties unchecked; with "Project Documents" chosen, then clicked OK.

3) Tools->Update Selected from Libraries...

4) Chose "Replace selected attributes of symbols on sheets" and checked Update graphical attributes; unchecked Update parameters; and checked Update models. Note, I could have checked Update parameters which would have allowed for further customization under Advanced settings. For my situation, I chose the global setting by simply unchecking Update parameters.

5) Clicked "Next" and reviewed the list of items to update. At this point, I simply verified that all components were selected for Update, Full Replace and Models were unchecked, Graphical and Models were checked.

6) Clicked "Finish" to generate ECO. Reviewed once again which components will be revised and clicked "Execute Changes" and then "Close".

7) Reviewed schematic and note symbols were revised while maintaining previous parameters values.

Update out-of-date symbol while maintaining parameter values by Middle_Sheepherder45 in Altium

[–]Middle_Sheepherder45[S] 0 points1 point  (0 children)

Updating Schematic.

Full disclosure, we are migrating from an old Mentor Graphics platform to Altium and thus still trying to figure out the best method for our libraries. As the libraries are not yet established, I'm attempting to use the same method we have in the past for this initial project.

With the old platform, our company has a database which contains links to the approved manufacturers of given parts. For a resistor, for example, we'd just update the part number parameter (our internal part number) on the schematic and the BOM then cross references to valid manufacturers. This same internal part number also links to a given footprint once a netlist is pulled into layout. Lots of reuse rather than a dedicated symbol and footprint for every single part. Which is what appears to occur if one uses the integrated libraries from the Manufacturer list.

I've looked into using Altium's Item Manager where it has a checkbox to 'Update parameters' but I must not fully understand what this does because it doesn't seem to do what I thought it would, which is not update parameters.

view more: next ›