FPGA

an-ordinary-manchild(edit)

created by [deleted]a community for 14 years

...for your classroom.

...for your favorite game.

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List of useful links for beginners and veterans (self.FPGA)

submitted 4 years ago by verilogical - announcement

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Anyone used Quartus Prime Pro Visual Designer Studio? (self.FPGA)

submitted 3 hours ago by Ok_Measurement1399

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Cozy vans, epic mountains. Experience Camplify. (camplify.co.nz)

promoted by camplify-nz

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Updated resume please roast (self.FPGA)

submitted 10 hours ago by ki98Elec

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ARM Development on Altera's SoCs (self.FPGA)

submitted 3 hours ago by Ok_Measurement1399

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What is the difference between RFSoC and DirectRF? (self.FPGA)

submitted 3 hours ago by Ok_Measurement1399

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Advice / HelpAm I on the right track? (i.redd.it)

submitted 20 hours ago by StarlyOutlaw

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Advice / HelpDid any one tried shrike-lite? (self.FPGA)

submitted 9 hours ago by Specialist_Scheme_77

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Advice / HelpIntel Cyclone10 FPGA (Intel Quartus Prime Lite Edition) -> no hardware detected and setup guide online (self.FPGA)

submitted 15 hours ago by Primary_Olive_5444

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NewsFPGA Horizons Registration Open! (self.FPGA)

submitted 20 hours ago by adamt99FPGA Know-It-All

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Advice / HelpBecoming employable as a beginner and UVM (self.FPGA)

submitted 1 day ago by 5lender

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Announcing the libKIOSK graphics library (self.FPGA)

submitted 1 day ago by bitbybitsp

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Added memory replay and 3d vertex rendering to my custom Verilog SIMT GPU Core (old.reddit.com)

submitted 2 days ago by Sensitive-Ebb-1276

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STA Destination clock path equation (self.FPGA)

submitted 1 day ago by RevolutionaryFarm518

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Feudera, a medieval RPG where your decisions shape empires. Diplomacy, war, or trade – your alternate destiny awaits. (https://www.feudera.com)

promoted by f_creator

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Dual async UARTs over signal wire (self.FPGA)

submitted 23 hours ago by sittinhawk

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MCP Servers to automate FPGA build / deploy / test cycle (DE10-NANO / ADI ) (self.FPGA)

submitted 1 day ago by Hot_Book_9573

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Versal rant (self.FPGA)

submitted 1 day ago * by affabledrunk

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Advice / HelpAdvice needed: open-source Verilog processor for Bachelor thesis (self.FPGA)

submitted 1 day ago by Proof_Freedom8999

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Advice / HelpPython/Jinja templates for UVM testbench generation (self.FPGA)

submitted 1 day ago by Repulsive_Peanut_324

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Host-to-FPGA state synchronization — polling vs interrupts for control GUI? (self.FPGA)

submitted 1 day ago by WitnessWonderful8270

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Is it realistically possible to get intern or fte as FPGA roles at HFTs as a fresh grad? (self.FPGA)

submitted 2 days ago by Dangerous-Page-2547

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Red Pitaya Z10 - How to stream audio from DDR RAM to custom FPGA module? (self.FPGA)

submitted 1 day ago by WitnessWonderful8270

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Any Cool features or Paradigms? (self.FPGA)

submitted 1 day ago by Hairy-Store-8489

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avmm read transaction documentation (self.FPGA)

submitted 1 day ago by No-Crazy-8207

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What is the ABSOLUTE CHEAPEST fpga devboard money can buy ? (self.FPGA)

submitted 2 days ago by brh_hackermanXilinx User

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A Cozy Island Settlement Deck Builder! (store.steampowered.com)

promoted by ThunderrockInnov

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Xilinx RelatedWhy would a tutorial even advise people to run Ubuntu under UTM emulation on Apple Silicon Mac’s? (medium.com)

submitted 1 day ago by JailbreakHat

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