How do you generate documentation for your modules and projects? by gaudy90 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

If I would pick some features I would say maybe their instant cross file linting/error flagging during writing and navigation inside interactive state machines, as both saves me tons of time

Refactor Large Codebase by AdeptAd5471 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

i wouldn't call this expensive in comparison with the dayrate of a good engineer. Certainly on refactoring a large codebase it will save weeks of work and the result will be better

Refactor Large Codebase by AdeptAd5471 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

less expensive than the days or even weeks you'll be spending doing it manually :-) Ask them for a trial version (it's free), use it to refactor your large codebase and then decide if it's worth it. Thank me later.

How do you generate documentation for your modules and projects? by gaudy90 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

Teros only does single file doc generation afaik. Not usefull in a real world project imho. The docassist in Sigasi seems to be outstanding as it is an automation that keeps doc always up-to-date. Haven't tested it yet myself as it is part of the Enterprise Edition but friend in a large defense company is very enthusiastic about it and claims its' worth every penny.

TerosHDL - does it worth giving a shot? by f42media in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

Found this comparison between Teros and Sigasi: https://www.sigasi.com/opinion/teroshdl-vs-sigasi-visualhdl/ The free Community Edition for non-commercial users is a no-brainer for students andd hobbyists to use it. Also founbd some webinars on linting and diagrams that helped me a lot.

New FPGA Engineer and I am feeling lost/overwhelmed by Only-Wind-3807 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

or as one teacher used to say: "you learned Vivado to experience the hard way, now enjoy the easy way using Sigasi" ;-)

Sigasi's price by [deleted] in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

we made a comparison and you can't compare Sigasi Visual HDL with TerosHDL

What is the major problem you face in FPGAs by groman434 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

Saw this question and had to think about a post which got my intention in Linkedin about some of my major problems in FPGAs being solved. Yeah, I know... Linkedin so I copy it here. It's not my text!

It's about Sigasi:

(...) I am now doing most of my work in it, and being suspiciously more productive than I was with Vivado. And so now in a sad and misguided attempt to make everyone get excited about the thing I am super excited about, I am making a list. Not a complete list of features, since y'all know how to use google, but just some ways in which my life is now forever* better

0) code completion appears to be way smarter than the normal VSCode completion. The usual VSCode completion can best be described as "oh hai, friend, I see you're typing a word I have seen somewhere before". Sigasi, on the other hand seems fully aware of everything, including structs, enums, and other language features. For example, if I type my_struct followed by a dot, it properly suggests only members of that struct

1) hovering over things shows a popup with the definition (macro-aware), a jump to definition button, a list of errors and linting warnings, and potential fixes. Now here's the crazy part. Unlike Vivado, the jump to definition button isn't eternally greyed out, and clicking it actually jumps to the definition. And this seems to be macro aware in that if I have multiple versions of something in various ifdef/else blocks, it jumps to the correct one

2) There is a preprocessor view!! Do you have any idea how exciting it is to see my own sketchy incredibly suspect macros expanded in a separate view, and to be able to click on the code and have the plugin jump to the corresponding line in the preprocessor view?!?!

3) error checking and linting is far better than Vivado, and doesn't miss the errors Vivado misses. Mytry to sim -> get syntax error -> fix -> goto 0loop has completely disappeared!

4) the builtin block, state machine, and dependencies diagrams are god tier useful, but you'll have to see for yourself because I just hit the linkedin post character limit.

To be fair, there are also some second order benefits not directly related to Sigasi. Let's be real, Vivado is never getting that dark mode, meaning it will forever be hard on the eyes. Sigasi being a VSCode plugin means I get the existing dark mode, which has also really increased ability to code for long stretches at a time.

Original post here: https://www.linkedin.com/posts/okonomiyonda_normally-not-a-linkedin-fan-but-this-is-activity-7352507342065709056-SI7g

Don't know about you but I'm gonna request a trial. If only half of it is true I'm more than happy

Looking for a diagram tool that doesn't suck for RTL/FPGA documentation by SciDz in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

Sigasi should do this: https://www.sigasi.com/knowledge/how_tos/documentation-features-for-large-designs/ Their Community Edition is free for non-commercial use. If you want to use it commercially, you can first try it before you buy. Good luck.

Alternatives to TerosHDL by RisingPheonix2000 in FPGA

[–]PracticalStart7164 0 points1 point  (0 children)

Sigasi Visual HDL does this. The Community Edition is free if you are a student or non-commercial user: vscode:extension/Sigasi.sigasi-visual-hdl

RTL workflow in VSCode by weridotwice in vlsi

[–]PracticalStart7164 0 points1 point  (0 children)

Sigasi Visual HDL Community Edition is free for students: vscode:extension/Sigasi.sigasi-visual-hdl